Binary Counters
Normally binary counters are used for counting the number of pulses coming at the input line in a specified time period.
The binary counters must possess memory since it has to remember its past states.
As the name suggests, it is a circuit which counts.The main purpose of the counter is to record the number of occurrence of some input.

Asynchronous (Ripple) Counters – The first flipflop is clocked by the external clock pulse, and then each successive flipflop is clocked by the Q or Q’ output of the previous flipflop.

Synchronous Counters – All memory elements are simultaneously triggered by the same clock.
Asynchronous or Ripple Counters
A twobit asynchronous counter is shown below in fig.1. The toggle(T) flipflops are being used. But we can use the JK flipflop also with J and K connected permanently to logic 1.
Fig.1
The external clock is connected to the clock input of the first flipflop (FFA) only and Q_{A} output is applied to the clock input of the next flipflop i.e. FFB.
So, FFA changes state at the falling edge of each clock pulse, but FFB changes only when triggered by the falling edge of the Q_{A} output of FFA.
Because of the inherent propagation delay through a flipflop, the transition of the input clock pulse and a transition of the Q_{A} output of FFA can never occur at exactly the same time.
Therefore, the flipflops cannot be triggered simultaneously, producing an asynchronous operation.
Operation
Initially let both the Flipflops be in the reset state i.e Q_{A}Q_{A}= 00
After 1st negative clock edge:
 As soon as the first negative clock edge is applied to FFA, Q_{A} will be equal to 1.
 Q_{A} is connected to clock input of FFB. Since Q_{A} has changed from 0 to 1, it is treated as the positive clock edge by FFB. So, there is no change in Q_{B} because FFB is a negative edge triggered FF.
Hence, Q_{B}Q_{A} = 01…………….After the first clock pulse
After 2nd negative clock edge:
 On the arrival of second negative clock edge, FFA toggles again and Q_{A} = 0.
 The change in Q_{A} acts as a negative clock edge for FFB. So it will also toggle, and Q_{B} will be 1.
Hence, Q_{B}Q_{A} = 10…………….After the second clock pulse
After 3rd negative clock edge:
 On the arrival of 3rd negative clock edge, FFA toggles again and Q_{A} become 1 from 0.
 Since this is a positive going change,FFB does not respond to it and remains inactive. So Q_{B} does not change and continues to be equal to 1.
Hence, Q_{B}Q_{A} = 11…………….After the third clock pulse
After 4th negative clock edge:
 On the arrival of 4th negative clock edge, FFA toggles again and Q_{A} become 1 from 0.
 This negative change in Q_{A} acts as clock pulse for FFB. Hence it toggles to change Q_{B} from 1 to 0.
Hence, Q_{B}Q_{A} = 00…………….After the fourth clock pulse
Truth Table
Synchronous counters
If the “clock” pulses are applied to all the flipflops in a counter simultaneously, then such a counter is called as synchronous counter.
2Bit Synchronous UP Counter
The J_{A} and K_{A} inputs of FFA are tied to logic 1. So FFA will work as a toggle flipflop. The J_{B} and K_{B }inputs are connected to Q_{A}.
Logic Diagram
Fig.2
Operation
Initially let both the FFs be in the reset state:
Q_{B}Q_{A} = 00…………….initially
After 1st negative clock edge
 As soon as the first negative clock edge is applied, FFA will toggle and Q_{A} will change from 0 to 1.
 But at the instant of application of negative clock edge, Q_{A} ,J_{B} = K_{B} =0 Hence FFB will not change its state. So Q_{B} will remain 0.
Hence, Q_{B}Q_{A} = 01…………….After the first clock pulse
After 2nd negative clock edge
 On the arrival of second negative clock edge, FFA toggles again and Q_{A} change from 1 to 0.
 But at this instant Q_{A} was 1. So J_{B} = K_{B}=1 and FFB will toggle. Hence Q_{B} changes from 0 to 1.
Hence, Q_{B}Q_{A} = 10…………….After the second clock pulse
After 3rd negative clock edge
 On application of the third falling clock edge, FFA will toggle from 0 to 1 but there is no change of state for FFB.
Hence, Q_{B}Q_{A} = 11…………….After the third clock pulse
After 4th negative clock edge
 On application of the next clock pulse, Q_{A} will change from 1 to 0 as Q_{B} will also change from 1 to 0.
Hence, Q_{B}Q_{A} = 00…………….After the fourth clock pulse
Classification of counters
Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows.
 Up counters
 Down counters
 Up/Down counters
UP/DOWN Counter
In the up/down counter, up counter and down counter are combined together to obtain an UP/DOWN counter.
A mode control (M) input is also provided to select either up or down mode.
A combinational circuit is required to be designed and used between each pair of flipflop in order to achieve the up/down operation.
Type of up/down counters:
 UP/DOWN ripple counters
 UP/DOWN synchronous counters
UP/DOWN Ripple Counters
In the UP/DOWN ripple counter all the FFs operate in the toggle mode.
So either T flipflops or JK flipflops are to be used.
The LSB flipflop receives clock directly. But the clock to every other FF is obtained from (Q or Q bar) output of the previous FF.
 UP counting mode (M=0): The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0).
 DOWN counting mode (M=1) : If M =1, then the Q bar output of the preceding FF is connected to the next FF. This will operate the counter in the down counting mode.
EXAMPLE
3bit binary up/down ripple counter.
 3bit : hence three FFs are required.
 UP/DOWN : So a mode control input is essential.
 For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one.
 For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of the next one.
 Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So connect Q bar to CLK.
BLOCK DIAGRAM
Fig.3
Fig.4
TRUTH TABLE
OPERATION
Case 1: With M = 0 (Up counting mode)
 If M = 0 and M bar = 1, then the AND gates 1 and 3 in fig. will be enabled whereas the AND gates 2 and 4 will be disabled.
 Hence Q_{A} gets connected to the clock input of FFB and Q_{B} gets connected to the clock input of FFC.
 These connections are same as those for the normal up counter. Thus with M = 0 the circuit work as an up counter.
Case 2: With M = 1 (Down counting mode)
 If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the AND gates 1 and 3 are disabled.
 Hence Q_{A} bar gets connected to the clock input of FFB and Q_{B} bar gets connected to the clock input of FFC.
 These connections will produce a down counter. Thus with M = 1 the circuit works as a down counter.
UP/DOWN Synchronous Counter
Example: Synchronous 3bit Up/Down Counter
Block Diagram
Fig.5
The circuit above is of a simple 3bit Up/Down synchronous counter using JK flipflops configured to operate as toggle or Ttype flipflops giving a maximum count of zero (000) to seven (111) and back to zero again.
Hence, the 3Bit counter advances upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0).
Modulus Counter (MODN Counter)
The 2bit ripple counter is called as MOD4 counter and 3bit ripple counter is called as MOD8 counter. So in general, an nbit ripple counter is called as moduloN counter. Where,MOD number = 2^{n}
TYPE OF MODULUS
 2bit up or down (MOD4)
 3bit up or down (MOD8)
 4bit up or down (MOD16)
Application of the counters
 Frequency counters
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator