Multiple Choice Questions and Answers on Microcontrollers and Applications(Part-2)
1) Which factor/s is/are supposed to have the equal values at both phases of transmission and reception levels with an intimation of error-free serial communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above
ANSWER: (d) All of the above
2) Which bits exhibit and signify the termination phase of the character transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above
ANSWER: (b) Status bits
3) Which two bits are supposed to be analyzed/tested for unity value (1) in SCON for the reception of byte in mode 1 serial communication?
a. RI & TI
b. REN & RB8
c. RI & REN
d. TI & RB8
ANSWER: (c) RI & REN
4) What is the bit transmitting or receiving capability of mode 1 in serial communication?
a. 8 bits
b. 10 bits
c. 11 bits
d. 12 bits
ANSWER: (b) 10 bits
5) Which pin in the shift register mode (Mode 0) of serial communication allow the data transmission as well as reception?
a. TXD
b. RXD
c. RB8
d. REN
ANSWER: (b) RXD
6) How is the baud rate determined on the basis of system clock frequency (fsc) in accordance to mode ‘0’ of serial communication?
a. (oscillator frequency) / 12
b. [2SMOD / 32] x (oscillator frequency) / [12 x (256 – (TH1)]
c. [2SMOD / 64] x (oscillator frequency)
d. 2SMOD/ 32 x (Timer 1 overflow rate)
ANSWER: (a) (oscillator frequency) / 12
7) Which serial modes possess the potential to support the multi-processor type of communication?
a. Modes 0 & 1
b. Modes 1 & 2
c. Modes 2 & 3
d. All of the above
ANSWER: (c) Modes 2 & 3
8) How does it become possible for 9th bit to differentiate the address byte from the data byte during the data transmission process in multiprocessor communication?
a. By recognizing 9th bit as ‘1’ for address byte & ‘0’ for data byte
b. By recognizing 9th bit as ‘0’ for address byte & ‘1’ for data byte
c. By recognizing 9th bit as ‘1’ for address as well as data bytes
d. By recognizing 9th bit as ‘0’ for address as well as data bytes
ANSWER: (a) By recognizing 9th bit as ‘1’ for address byte & ‘0’ for data byte
9) Which byte has the capability to interrupt the slave when SM2 bit is assigned to be ‘1’ after the initialization process in the multiprocessor mode of communication?
a. Address byte
b. Data byte
c. Both a & b
d. None of the above
ANSWER: (a) Address byte
10) Which bits of opcode specify the type of registers to be used in the register addressing mode?
a. LSB
b. MSB
c. Both a & b
d. None of the above
ANSWER: (a) LSB
11) Which base-register is preferred for address calculation of a byte that is to be accessed from program memory by base-register plus register-indirect addressing mode?
a. DPTR
b. PSW
c. PCON
d. All of the above
ANSWER: (a) DPTR
12) What does the symbol ‘#’ represent in the instruction MOV A, #55H?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype
ANSWER: (c) Immediate datatype
13) How many single byte, two-byte and three-byte instructions are supported by MCS-51 from the overall instruction set?
a. 55 – single byte, 35 two-byte & 21 three-byte instructions
b. 50 – single byte, 30 two-byte & 31 three-byte instructions
c. 42 – single byte, 45 two-byte & 24 three-byte instructions
d. 45 – single byte, 45 two-byte & 17 three-byte instructions
ANSWER: (d) 45 – single byte, 45 two-byte & 17 three-byte instructions
14) What kind of PSW flags remain unaffected by the data transfer instructions?
a. Auxillary Carry Flags
b. Overflow Flags
c. Parity Flags
d. All of the above
ANSWER: (d) All of the above
15) Which instruction should be adopted for moving an accumulator to the register from the below mentioned mnemonics?
a. MOV A, Rn
b. MOV A, @ Ri
c. MOV Rn, A
d. MOV direct, A
ANSWER:(c) MOV Rn, A
16) What does the instruction XCHD A, @Ri signify during the data transfer in the program execution?
a. Exchange of register with an accumulator
b. Exchange of direct byte with an accumulator
c. Exchange of indirect RAM with an accumulator
d. Exchange of low order digit indirect RAM with an accumulator
ANSWER: (d) Exchange of low order digit indirect RAM with an accumulator
17) Which flag allow to carry out the signed as well as unsigned addition and subtraction operations?
a. CY
b. OV
c. AC
d. F0
ANSWER: (b) OV
18) How many bytes are supposed to get occupied while subtracting indirect RAM from an accumulator along with borrow under the execution of SUBB A, @Ri?
a. 1
b. 2
c. 3
d. 4
ANSWER:(a) 1
19) What can be the oscillator period for the multiplication operation of A & B in accordance to 16-bit product especially in B:A registers?
a. 12
b. 24
c. 36
d. 48
ANSWER: (d) 48
20) Which form of instructions also belong to the category of logical instructions in addition to bitwise logical instructions?
a. Single-operand instructions
b. Rotate instructions
c. Swap instructions
d. All of the above
ANSWER: (d) All of the above
21) Which rotate instruction/s has an ability to modify CY flag by moving the bit-7 & bit-0 respectively to an accumulator?
a. RR & RL
b. RLC & RRC
c. RR & RRC
d. RL & RLC
ANSWER: (b) RLC & RRC
22) Which among the single operand instructions complement the accumulator without affecting any of the flags?
a. CLR
b. SETB
c. CPL
d. All of the above
ANSWER: (c) CPL
23) Match the following
a. JC rel ——————– 1. Jump if direct bit is set & clear bit
b. JNC rel —————— 2. Jump if direct bit is set
c. JB bit, rel ————— 3. Jump if direct bit is not set
d. JBC bit, rel ———— 4. Jump if carry is set
e. JNB bit, rel ————- 5. Jump if carry is not set
a. A-3, B-2, C-1, D-4, E-5
b. A-5, B-2, C-4, D-1, E-3
c. A-5, B-4, C-3, D-2, E-1
d. A-4, B-5, C-2, D-1, E-3
ANSWER: (d) A-4, B-5, C-2, D-1, E-3
24) What is the possible range of transfer control for 8-bit relative address especially in 2’s complement form with respect to the first byte of preceding instruction?
a. -115 to 132 bytes
b. -130 to 132 bytes
c. -128 to 127 bytes
d. -115 to 127 bytes
ANSWER:(c) -128 to 127 bytes
25) Which among the category of program branching instructions allow 16 bit address to be specified & can jump anywhere within 64K block of program memory?
a. Long jumps (LJMP)
b. Short jumps (SJMP)
c. Absolute jumps (AJMP)
d. All of the above
ANSWER: (a) Long jumps (LJMP)
26) Consider the below mentioned statements. Which among them is /are approved to be incorrect in case of calling instructions of program branching?
a. Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program memory block
b. Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory block
c. Short call instructions specify 16-bit address and subroutine within 4K program memory block
d. All long call and short call instructions specify 11 bit address and the calling subroutine within 16K program memory block
a. Only A
b. B & D
c. A & C
d. C & D
ANSWER: (d) C & D
27) Match the following instruction mnemonics with their description.
a. CJNE A,direct,rel ———— 1. Compare immediate to indirect and Jump if not equal
b. CJNE A,#data,rel ———— 2. Compare direct byte to accumulator and Jump if not equal
c. CJNE @Ri, #data,rel ——- 3. Compare immediate to register and Jump if not equal
d. CJNE Rn, # data rel ——– 4. Compare immediate to accumulator and Jump if not equal
a. A-1, B-2, C-3, D-4
b. A-2, B-4, C-1, D-3
c. A-4, B-3, C-2, D-1
d. A-2, B-4, C-3, D-1
ANSWER: (b) A-2, B-4, C-1, D-3
28) What is the correct chronological order of the following steps involved in the LCALL operation?
1. Load the value of 16-bit destination address to program counter
2. Increment of the program counter by value ‘3’
3. Storage of the higher byte of program counter on the stack
4. Increment of the stack pointer by value’1′
5. Storage of the lower byte of program counter on the stack
6. Increment in the value of stack pointer
a. 5, 3, 1, 6, 2, 4
b. 1, 3, 2, 5, 4, 6
c. 2, 4, 5, 6, 3, 1
d. 5, 3, 6, 2, 4, 1
ANSWER: (c) 2, 4, 5, 6, 3, 1
29) What is the status of stack pointer for the execution of PUSH and POP operations?
a. It gets post-decremented for PUSH & pre-incremented for POP
b. It gets pre-incremented for PUSH & post-decremented for POP
c. It gets pre-incremented for PUSH as well as POP
d. It gets post-decremented for PUSH as well as POP
ANSWER: (b) It gets pre-incremented for PUSH & post-decremented for POP
30) Which instructions contribute to an effective adoption or utilization of stack memory which usually plays a crucial role in storage of intermediate results?
a. ACALL
b. RETI
c. PUSH & POP
d. All of the above
ANSWER: (d) All of the above
31) Which functioning element of microcontroller generate and transmit the address of instructions to memory through internal bus?
a. Instruction Decoding Unit
b. Timing and Control Unit
c. Program Counter
d. Arithmetic Logic Unit
ANSWER: (c) Program Counter
32) How does the microcontroller communicate with the external peripherals/memory?
a. via I/O ports
b. via register arrays
c. via memory
d. All of the above
ANSWER: (a) via I/O ports
33) Why do the microprocessors possess very few bit manipulating instructions?
a. Because they mostly operate on bits/ word data
b. Because they mostly operate on byte/word data
c. Both a & b
d. None of the above
ANSWER: (b) Because they mostly operate on byte/word data
34) Which minimum mode signal is used for demultiplexing the data and address lines with the assistance of an external latch in a microprocessor while accessing memory segment?
a. INTA
b. DTE
c. HOLD
d. ALE
ANSWER: (d) ALE
35) Which word size is approved to be of greater importance for performing the small computational tasks along with its storage usability feature adopted by ASCII code?
a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit
ANSWER: (b) 8-bit
36) Which among the below stated statements does not exhibit the characteristic feature of 16-bit microcontroller?
a. Large program & data memory spaces
b. High speed
c. I/O Flexibility
d. Limited Control Applications
ANSWER: (d) Limited Control Applications
37) Which microcontrollers offer the provisional and salient software features of fault handling capability, interrupt vector efficiency and versatile addressing?
a. TMS 1000 (4 bit)
b. TMS 7500 (8 bit)
c. Intel 8096 (16 bit)
d. Intel 80960 (32 bit)
ANSWER: (d) Intel 80960 (32 bit)
38) Which category of microcontrollers acquire the complete hardware configuration on its chip so as to run the particular application?
a. Embedded Memory Microcontrollers
b. External Memory Microcontrollers
c. Both a & b
d. None of the above
ANSWER: (a) Embedded Memory Microcontrollers
39) External Memory Microcontrollers can overcome the limitations of insufficient in-built program and data memory by allowing the connections of external memory using _________
a. Serial Port Pins as address and data lines
b. Parallel Port Pins as address and data lines
c. Parallel Port Pins as address and control lines
d. Serial Port Pins as address and control lines
ANSWER: (b) Parallel Port Pins as address and data lines
40) How are the address and data buses removed in external memory type of microcontrollers?
a. Through demultiplexing by external latch & ALE signal
b. Through demultiplexing by external latch & DLE signal
c. Through multiplexing by external latch & DLE signal
d. Through multiplexing by external latch & ALE signal
ANSWER: (d) Through multiplexing by external latch & ALE signal
41) What are the significant designing issues/factors taken into consideration for RISC Processors?
a. Simplicity in Instruction Set
b. Pipeline Instruction Optimization
c. Register Usage Optimization
d. All of the above
ANSWER: (d) All of the above
42) What does the compact and uniform nature of instructions in RISC processors facilitate to?
a. Compiler optimization
b. Pipelining
c. Large memory footprints
d. None of the above
ANSWER: (b) Pipelining
43) Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?
a. Local Register
b. Temporary Register
c. Parameter Register
d. All of the above
ANSWER: (b) Temporary Register
44) Which architectural scheme has a provision of two sets for address & data buses between CPU and memory?
a. Harvard architecture
b. Von-Neumann architecture
c. Princeton architecture
d. All of the above
ANSWER: (a) Harvard architecture
45) Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture by most of the DSPs for streaming data?
a. Greater memory bandwidth
b. Predictable nature of bandwidth
c. Both a & b
d. None of the above
ANSWER: (c ) Both a & b
46) Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program and data fetching purposes?
a. Time Division Multiplexing
b. Frequency Division Multiplexing
c. Statistical Time Division Multiplexing
d. Code Division Multiplexing
ANSWER: (a) Time Division Multiplexing
47) Which feature deals with the fetching of next instruction during the execution of current instruction irrespective of the memory access?
a. Fetching
b. Pre-fetching
c. Fetch & Decoding
d. All of the above
ANSWER: (b) Pre-fetching
48) What are the essential tight constraint/s related to the design metrics of an embedded system?
a. Ability to fit on a single chip
b. Low power consumption
c. Fast data processing for real-time operations
d. All of the above
ANSWER: (d) All of the above
49) Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system?
a. System
b. Behaviour
c. RT
d. Logic
ANSWER: (b) Behaviour
50) Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system’s environment by computing specific results for real-time applications without any kind of postponement?
a. Single-functioned Characteristics
b. Tightly-constraint Characteristics
c. Reactive & Real time Characteristics
d. All of the above
ANSWER: (c ) Reactive & Real time Characteristics
51) Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
a. CD & IR
b. DSR & DTR
c. RTS & CTS
d. None of the above
ANSWER: (c) RTS & CTS
52) Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process?
a. XON/ XOFF
b. DCD & GND
c. TxD & RxD
d. All of the above
ANSWER: (a )XON/ XOFF
53) Match the following registers with their functions :
a. Line Status Register ——————– 1. Set Up the communication parameters
b. Line Control Register —————— 2. Sharing of similar addresses
c. Transmit & Receive Buffers ——— 3. Status Determination of Tx & Rr
a. A-2, B-1, C-3
b. A-1, B-2, C-3
c. A-3, B-1, C-2
d. A-3, B-2, C-1
ANSWER: (c ) A-3, B-1, C-2
54) Which protocol standard of serial communication specify the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
a. RS232
b. RS2485
c. RS422
d. RS423
ANSWER: ( b ) RS2485
55) What is the maximum device handling capacity of serial standard protocol RS485 in terms of drivers and receivers on a single line?
a. 8
b. 10
c. 16
d. 32
ANSWER: (d) 32
56) Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware handshake line during each time of the data transmission?
a. RTS Control
b. Send Data Control
c. Tri-State Control
d. Bit-wise Enable Timing Control
ANSWER: (b )Send Data Control
57) What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications?
a. Bus Master
b. Bus Slaves
c. Bus Drivers
d. Bus Data Carriers
ANSWER: (a) Bus Master
58) What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carrying the information between the devices?
a. Uni-directional
b. Bi-directional
c. Multi-directional
d. None of the above
ANSWER: (b) Bi-directional
59) Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus?
a. Master in master-transmit mode & Slave in slave-receive mode
b. Slave in slave-transmit mode & Master in master-receive mode
c. Master in master-transmit mode as well as master-receive mode
d. Slave in slave-transmit mode as well as slave-receive mode
ANSWER: (a) Master in master-transmit mode & Slave in slave-receive mode
60) Which processor has the necessity of manual optimization for the generation of assembly language code especially for the embedded systems?
a. RISC
b. CISC
c. Both a & b
d. None of the above
ANSWER: (b) CISC
