Multiple Choice Questions and Answers on Analog and Digital Converters
Multiple Choice Questions and Answers on Analog and Digital Converters
In addition to reading the questions and answers on my site, I would suggest you to check the following, on amazon, as well:
- Question Bank in Electronics & Communication Engineering by Prem R Chadha
- A Handbook on Electronics Engineering – Illustrated Formulae & Key Theory Concepts
Q1. The practical use of binary-weighted digital-to-analog converters is limited to:
a) R/2R ladder D/A converters
b) 4-bit D/A converters
c) 8-bit D/A converters
d) op-amp comparators
Answer : b
Q2. What is the resolution of a digital-to-analog converter (DAC)?
a) It is the comparison between the actual output of the converter and its expected output.
b) It is the deviation between the ideal straight-line output and the actual output of the converter.
c) It is the smallest analog output change that can occur as a result of an increment in the digital input.
d) It is its ability to resolve between forward and reverse steps when sequenced over its entire range.
Answer : c
Q3. Which of the following is a type of error associated with digital-to-analog converters (DACs)?
a) nonmonotonic error
b) incorrect output codes
c) offset error
d) nonmonotonic and offset error
Answer : d
Q4. A 4-bit R/2R digital-to-analog (DAC) converter has a reference of 5 volts. What is the analog output for the input code 0101.
a) 0.3125 V
b) 3.125 V
c) 0.78125 V
d) –3.125 V
Answer : b
Q5. A binary-weighted digital-to-analog converter has an input resistor of 100 k
. If the resistor is connected to a 5 V source, the current through the resistor is:
a) 50 
A
b) 5 mA
c) 500 A
d) 50 mA
Answer : a
Q6. In a flash analog-to-digital converter, the output of each comparator is connected to an input of a:
a) decoder
b) priority encoder
c) multiplexer
d) demultiplexer
Answer : b
Q7. Which is not an analog-to-digital (ADC) conversion error?
a) differential nonlinearity
b) missing code
c) incorrect code
d) offset
Answer : a
Q8. Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:
a) sample and hold the output of the binary counter during the conversion process
b) stabilize the comparator’s threshold voltage during the conversion process
c) stabilize the input analog signal during the conversion process
d) sample and hold the D/A converter staircase waveform during the conversion process
Answer : c
Q9. The resolution of a 0–5 V 6-bit digital-to-analog converter (DAC) is:
a) 63%
b) 64%
c) 1.56%
d) 15.6%
Answer : c
Q10. What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a binary-weighted digital-to-analog DAC converter?
a) It only uses two different resistor values.
b) It has fewer parts for the same number of inputs.
c) Its operation is much easier to analyze.
d) The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot.
Answer : a
Q11. A binary-weighted digital-to-analog converter has a feedback resistor, Rf, of 12 k. If 50 A of current is through the resistor, the voltage out of the circuit is:
a) 0.6 V
b) –0.6 V
c) 0.1 V
d) –0.1 V
Answer : b
Q12. The primary disadvantage of the flash analog-to digital converter (ADC) is that:
a) it requires the input voltage to be applied to the inputs simultaneously
b) a long conversion time is required
c) a large number of output lines is required to simultaneously decode the input voltage
d) a large number of comparators is required to represent a reasonable sized binary number
Answer : d
Q13. The difference between analog voltage represented by two adjacent digital codes, or the analog step size, is the:
a) quantization
b) accuracy
c) resolution
d) monotonicity
Answer : c
Q14. Which of the following is an example of an Analog-to-Digital Converter (ADC)?
a) R-2R Ladder Network
b) Flash Converter
c) Weighted Resistor DAC
d) Integrator
Answer: b
Q15. What is the main function of a Digital-to-Analog Converter (DAC)?
a) Converts binary data into decimal numbers
b) Converts digital signals into equivalent analog signals
c) Amplifies analog signals
d) Converts analog signals into digital signals
Answer: b
Q16. In a DAC, the resolution depends on:
a) The number of input bits
b) The reference voltage only
c) The clock frequency
d) Both input voltage and output current
Answer: a
Q17. Which ADC has the fastest conversion speed?
a) Flash ADC
b) Successive Approximation ADC
c) Dual Slope ADC
d) Sigma-Delta ADC
Answer: a
Q18. A Successive Approximation Register (SAR) ADC works on the principle of:
a) Simultaneous comparison
b) Voltage integration
c) Binary search algorithm
d) Counting pulses
Answer: c
Q19. In Dual-Slope ADC, conversion time depends on:
a) Number of bits
b) Input signal frequency
c) Integration period
d) Reference current only
Answer: c
Q20. Which of the following is NOT a type of ADC?
a) Flash ADC
b) R-2R Ladder ADC
c) Dual-Slope ADC
d) Successive Approximation ADC
Answer: b
Q21. Which of the following converters provides the highest accuracy but slower speed?
a) Flash ADC
b) Dual-Slope ADC
c) SAR ADC
d) Tracking ADC
Answer: b
Q22. A 10-bit ADC has how many discrete output levels?
a) 512
b) 1024
c) 1000
d) 2048
Answer: b
Q23. In DACs, monotonicity means:
a) Output always increases or remains constant as input increases
b) Output decreases when input increases
c) Output oscillates with input
d) None of the above
Answer: a
Q24. Which DAC is the fastest?
a) Weighted Resistor DAC
b) R-2R Ladder DAC
c) Current Steering DAC
d) Integrating DAC
Answer: c
Q25. Which of the following is NOT used in DACs?
a) Weighted Resistor Method
b) R-2R Ladder
c) Dual-Slope Integration
d) Current Steering
Answer: c
Q26. Settling time in a DAC refers to:
a) The delay before input is accepted
b) The time taken for output to stabilize within an error band
c) The clock pulse width
d) The conversion rate
Answer: b
Q27. A 4-bit DAC with reference voltage 5 V has an LSB (step size) of:
a) 0.3125 V
b) 0.25 V
c) 0.5 V
d) 1 V
Answer: a
Q28. Conversion time of Dual-Slope ADC depends on:
a) Clock frequency only
b) Input voltage
c) Integration period
d) Number of bits
Answer: c
Q29. Quantization error in an ADC is:
a) ±0.5 LSB
b) ±1 LSB
c) ±2 LSB
d) ±n LSB
Answer: a
Q30. A Sigma-Delta ADC is best suited for:
a) High-speed applications
b) Low-speed, high-resolution applications
c) Video signals
d) Multiplexing
Answer: b
Q31. The flash ADC requires:
a) 1 comparator
b) n comparators
c) 2^n – 1comparators
d) n² comparators
Answer: c
Q32. In a tracking ADC, conversion is based on:
a) Parallel comparison
b) Successive approximation
c) Up/Down counter
d) Dual slope integration
Answer: c
Q33. Which of the following parameters affects both ADC and DAC?
a) Resolution
b) Linearity
c) Settling time
d) All of the above
Answer: d
Q34. Nyquist theorem states:
a) Sampling frequency ≥ Signal frequency
b) Sampling frequency ≥ 2 × Signal frequency
c) Sampling frequency ≤ Signal frequency
d) Sampling frequency = Signal frequency
Answer: b
Q35. The process of mapping continuous signals into discrete steps is called:
a) Modulation
b) Quantization
c) Demodulation
d) Amplification
Answer: b
Q36. Which converter is used in digital oscilloscopes?
a) Flash ADC
b) SAR ADC
c) Dual-Slope ADC
d) R-2R Ladder DAC
Answer: a
Q37. Differential Non-Linearity (DNL) error occurs when:
a) Step size is not constant
b) Gain error exists
c) Offset error exists
d) Resolution decreases
Answer: a
Q38. Integral Non-Linearity (INL) measures:
a) Deviation from ideal straight line transfer
b) Offset at zero
c) Gain error at full scale
d) Step size variation
Answer: a
Q39. Sample-and-Hold circuits are used in ADCs to:
a) Amplify the signal
b) Maintain constant input during conversion
c) Reduce quantization error
d) Speed up conversion
Answer: b
Q40. A DAC with poor linearity will cause:
a) Faster response
b) Distortion in output
c) Reduced resolution
d) Increased quantization noise
Answer: b
Q41. A higher bit ADC has:
a) Higher resolution
b) Lower resolution
c) Faster conversion always
d) Less accuracy
Answer: a
Q42. In audio systems, which ADC/DAC combination is common?
a) Flash ADC and Weighted DAC
b) Sigma-Delta ADC and Current-Steering DAC
c) SAR ADC and R-2R DAC
d) Dual-Slope ADC and R-2R DAC
Answer: b
Q43. The step size of an 8-bit ADC with 5 V reference is:
a) 5/255 V
b) 5/256 V
c) 5/512 V
d) 5/1024 V
Answer: a
Q44. In an ideal DAC, output error is:
a) Zero
b) ±0.5 LSB
c) ±1 LSB
d) Depends on reference
Answer: a
Q45. Slew rate limitation in DACs causes:
a) Distortion at high frequencies
b) Improved accuracy
c) Faster settling
d) Lower resolution
Answer: a
Q46. An ADC with 1 V reference and 8-bit resolution has LSB value:
a) 1/256 V
b) 1/255 V
c) 1/512 V
d) 2/256 V
Answer: a
Q47. Which ADC provides best noise immunity?
a) Flash
b) SAR
c) Dual-Slope
d) Tracking
Answer: c
Q48. In successive approximation ADC, each step compares input with:
a) Fixed reference
b) Variable reference from DAC
c) Comparator threshold
d) Clock pulse
Answer: b
Q49. Which of the following applications needs very high-speed ADCs?
a) Digital voltmeter
b) Video signal digitization
c) Audio signal processing
d) Temperature measurement
Answer: b
Q50. The primary disadvantage of flash ADCs is:
a) Slow speed
b) High cost and power consumption
c) Low resolution
d) Complex binary search
Answer: b
