Monolithic or Planar Processes of IC Production

Monolithic or Planar Processes of IC Production


A monolithic IC is one in which all circuit components and their interconnections are formed on a single thin wafer, called the substrate. The basic production processes for the monolithic ICs are given below:

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1.      Crystal Growth of Substrate

It is the bottom most layer that serves as the body or substrate upon which the complete IC is built. A typical P-type crystal is grown in dimensions of 250 mm length and 25 mm diameter, as shown in fig 1 (a).

p-type silicon crystal

Fig 1 (a): P-Type    Silicon Crystal

Silicon is preferred because its characteristics are more suitable for manufacturing of ICs. The crystal is then cut by a diamond saw into thin slices called wafers. These wafers after being lapped and polished to mirror finish serve as the base or substrate on which hundreds of ICs are produced. The enlarged view of circular wafer is shown in fig 1(b).


Fig 1 (b) : Wafer

The wafer may also be rectangular in shape as shown in fig 2 .

rectangular silicon wafer

Fig 2 : Rectangular Wafer

2.      Epitaxial Growth

On the high resistivity P-type substrate a low resistivity 25 µm thick layer of N-type is epitaxially grown.

For this purpose, the wafers are placed in a diffusion furnace at 1,200oC and a gas mixture of silicon atoms and pentavalent atoms is passed over the wafers.

This forms a thin layer of N-type semiconductor on the heated surface of the substrate, as shown in fig 3.

epitaxial growth

Fig 2

It is this epitaxial layer that all active and passive components of an IC are formed. This layer ultimately becomes the collector for a transistor or an element for a diode or a capacitor. The resistivity of P-type substrate for NA = 1.4 x 1021 atoms/m3 is typically 10 Ω-cm. The resistivity of N-type epitaxial layer is suitably chosen in the range of 0.1 – 0.5 Ω-cm. This layer is finally polished and cleaned.

3.      Oxidation

In order to prevent the contamination of the epitaxial layer, a thin layer of SiO2 is formed over the entire surface, as illustrated in fig 3 .


Fig 3

The SiO2 layer is grown by exposing the epitaxial layer to an oxygen atmosphere to about 1,000oC. This surface layer of SiO2 will prevent any impurities from entering the N-type epitaxial layer. However, selective etching of this layer will permit the diffusion of the proper impurity into designed areas of the N-type epitaxial region of the silicon wafer.

4.      Photolithographic Process

The monolithic technique requires the selective removal of the silicon-dioxide (SiO2) to form openings through which impurities may be diffused, if required. The photolithographic process is shown in fig. 4 is used for this purpose.

Photolithiographic process

Fig 4

During the process the wafer is coated with a thin layer of photo-sensitive material, commonly known as photo-resist (such as Kodak photoresist KPR).

A  layout of the desired pattern of openings or windows is made on the top and then reduced photographically. This negative, or stencil, of the required dimensions is placed as a mask over the photoresist, as illustrated in fig 4.

This wafer surface with mask is then exposed to the ultraviolet light. Due to ultraviolet light, the photoresists below the transparent portions of the mask becomes polymerised.

The mask is now removed, and the wafer is developed by using a chemical like trichloroethylene.

The chemical dissolves the unpolymerised portions of the photoresist film and leaves the surface as shown in fig 5.

photolithigraphic process1

Fig 5

The oxide not covered by polymerised photoresists is then removed by immersing the chip in an etching solution of the acid. After etching and diffusion of impurities, the resist mask is stripped off with a chemical solvent like hot sulphuric acid (H2SO4) and by means of a mechanical abrasion process. The appropriate impurities are then diffused through oxide free windows.

5.      Isolation Diffusion

SiO2 layer is removed from the desired areas (four selected portions from the wafer, as illustrated in fig 6 using photolithographic etching process explained above.

isolation diffusion

Fig 6

The remaining SiO2 layer serves as mask for the diffusion of acceptor impurities. The wafer is now subjected to isolation diffusion at a suitably high temperature and for appropriate time period allowing P-type impurity (boron in this case) to penetrate into the N-type epitaxial layer through the openings in SiO2 layer and ultimately reach the P-type substrate.

The temperature and time period of diffusion are required to be carefully controlled. The process results in formation of N-type regions, called the isolation islands. Then name is given as they are separated by back-to-back P-N junctions.

Their purpose is to permit electrical isolation between various components of IC.

Each electrical element is later on formed in a separate isolation island. The bottom of the N-type isolation island ultimately forms the collector of a P-N-P transistor.

The P-type substrate is always kept negative w.r.t the isolation islands and provided with reverse bias at P-N junctions. If P-N junctions are forward biased, the isolation will get lost.

Isolation diffusion is controlled so as to cause high acceptor concentration P+ (typically NA = 5 x 1026 atoms/m3) in the region between the isolation islands.

Two adjoining isolation islands are connected to the P-type substrate by a barrier capacitance or transition capacitance.

This is undesirable and is called the parasitic capacitance. It adversely affects the performance of the IC and puts a limitation on its use.

The parasitic capacitance has two components; the capacitance C1 from the bottom of the N-type region to the substrate and capacitance C2 from the sidewalls of the isolation islands to the P-type region.

The bottom component C2 is essentially due to step junction formed by epitaxial growth and, therefore, varies as the square root of the voltage V between the isolation region and substrate.

The sidewall capacitance C2 is associated with a diffused graded junction and so varies as V-1/2. The total capacitance is of the order of a few pF.

6.      Base Diffusion

During this process a new layer of SiO2 is formed over the wafer. The new pattern of openings depending upon the circuit needs. In these openings P-type impurities like Boron are diffused under regulated environments to form p-regions. This forms the base region of an N-P-N transistor or as well as resistors, the anode of diode, and junction capacitor. In this case, the diffusion time is so controlled that the P-type impurities do not reach the substrate. The resistivity of the base layer is usually much higher than that of the isolation regions.

base diffusion

Fig 7

7.      Emitter Diffusion

A layer of SiO2 is again formed over the entire surface and openings in the P-type regions, as shown in fig 8, are formed again by employing masking and etching processes. The N-type impurities like phosphorous are then diffused through these windows under controlled environments to form the transistor emitters, the cathode regions for diodes, and junction capacitors. Additional windows (such as W1 and W2 in fig 8) are usually made into the N-regions to permit aluminium metallic connections.

emitter diffusion

Fig 8

8.      Aluminium Metalization

For making electrical connection between various components of the IC, several window are opened on a newly created SiO2 layer. Now a thin layer of aluminium is deposited on the entire top surface.

Further, photoresist technique is used to etch away all the unwanted aluminium areas.

The structure then provides the connected strips to which leads are attached, as illustrated in fig 9 .

Aluminium metalization

Fig 9

9.      Scribing and Mounting

In practice, a large number (several hundreds) of identical ICs are manufactured simultaneously on a silicon wafer. After the completion of the metalization process, the wafer is scribed with a diamond-tipped tool and separated into individual chips. Each chip is then mounted on a ceramic wafer and is attached to a suitable header. Next the package leads are connected to the IC chip by stich bonding of 25 micron aluminium or gold wire from the terminal pad on the IC chip to the package lead.