Multiple Choice Questions and Answers on Microcontrollers and Applications
1) Which operations are performed by the bit manipulating instructions of boolean processor?
a. Complement bit
b. Set bit
c. Clear bit
d. All of the above
ANSWER: (d) All of the above
2) Which data memory control and handle the operation of several peripherals by assigning them in the category of special function registers?
a. Internal on-chip RAM
b. External off-chip RAM
c. Both a & b
d. None of the above
ANSWER: (a) Internal on-chip RAM
3) Why is the speed accessibility of external data memory slower than internal on-chip RAM?
a. Due to multiplexing of lower order byte of address-data bus
b. Due to multiplexing of higher order byte of address-data bus
c. Due to demultiplexing of lower order byte of address-data bus
d. Due to demultiplexing of higher order byte of address-data bus
ANSWER: (a) Due to multiplexing of lower order byte of address-data bus
4) Which control signal/s is/are generated by timing and control unit of 8051 microcontroller in order to access the off-chip devices apart from the internal timings?
a. ALE
b. PSEN
c. RD & WR
d. All of the above
ANSWER: (d) All of the above
5) Which register usually store the output generated by ALU in several arithmetic and logical operations?
a. Accumulator
b. Special Function Register
c. Timer Register
d. Stack Pointer
ANSWER: (a) Accumulator
6) Why is CHMOS technology preferred over HMOS technology for designing the devices of MCS-51 family?
a. Due to higher noise immunity
b. Due to lower power consumption
c. Due to higher speed
d. All of the above
ANSWER: (d) All of the above
7) Which condition approve to prefer the EPROM/ROM versions for mass production in order to prevent the external memory connections?
a. size of code < size of on-chip program memory
b. size of code > size of on-chip program memory
c. size of code = size of on-chip program memory
d. None of the above
ANSWER: (a) size of code < size of on-chip program memory
8) Which among the below mentioned devices of MCS-51 family does not possess two 16 -bit timers/counters?
a. 8031
b. 8052
c. 8751
d. All of the above
ANSWER: (b) 8052
9) Which characteristic/s of accumulator is /are of greater significance in terms of its functionality?
a. Ability to store one of the operands before the execution of an instruction
b. Ability to store the result after the execution of an instruction
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
10) Which general purpose register holds eight bit divisor and store the remainder especially after the execution of division operation?
a. A-Register
b. B-Register
c. Registers R0 through R7
d. All of the above
ANSWER: (b) B-Register
11) How many registers can be utilized to write the programs by an effective selection of register bank in program status word (PSW)?
a. 8
b. 16
c. 32
d. 64
ANSWER: (c) 32
12) Which operations are performed by stack pointer during its incremental phase?
a. Push
b. Pop
c. Return
d. All of the above
ANSWER: (a) Push
13) Which is the only register without internal on-chip RAM address in MCS-51?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. Timer Register
ANSWER: (b) Program Counter
14) What kind of instructions usually affect the program counter?
a. Call & Jump
b. Call & Return
c. Push & Pop
d. Return & Jump
ANSWER: (a) Call & Jump
15) What is the default value of stack once after the system undergoes the reset condition?
a. 07H
b. 08H
c. 09H
d. 00H
ANSWER:(a) 07H
16) Which bit/s play/s a significant role in the selection of a bank register of Program Status Word (PSW)?
a. RS1
b. RS0
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
17) Which flags represent the least significant bit (LSB) and most significant bit (MSB) of Program Status Word (PSW) respectively?
a. Parity Flag & Carry Flag
b. Parity Flag & Auxiliary Carry Flag
c. Carry Flag & Overflow Flag
d. Carry Flag & Auxiliary Carry Flag
ANSWER: (a) Parity Flag & Carry Flag
18) Which register bank is supposed to get selected if the values of register bank select bits RS1 & Rs0 are detected to be ‘1’ & ‘0’ respectively?
a. Bank 0
b. Bank 1
c. Bank 2
d. Bank 3
ANSWER: (c) Bank 2
19) It is possible to set the auxiliary carry flag while performing addition or subtraction operations only when the carry exceeds _______
a. 1st bit
b. 2nd bit
c. 3rd bit
d. 4th bit
ANSWER: (c) 3rd bit
20) Which locations of 128 bytes on-chip additional RAM are generally reserved for special functions?
a. 80H to 0FFH
b. 70H to 0FFH
c. 90H to 0FFH
d. 60H to 0FFH
ANSWER: (a) 80H to 0FFH
21) Which commands are used for addressing the off-chip data and associated codes respectively by data pointer?
a. MOVX & MOVC
b. MOVY & MOVB
c. MOVZ & MOVA
d. MOVC & MOVY
ANSWER: (a) MOVX & MOVC
22) Which instruction find its utility in loading the data pointer with 16 bits immediate data?
a. MOV
b. INC
c. DEC
d. ADDC
ANSWER: (a) MOV
23) What is the maximum capability of addressing the off-chip data memory & off-chip program memory in a data pointer?
a. 8K
b. 16K
c. 32K
d. 64K
ANSWER: (d) 64K
24) Which among the below stated registers does not belong to the category of special function registers?
a. TCON & TMOD
b. TH0 & TL0
c. P0 & P1
d. SP & PC
ANSWER: (d) SP & PC
25) Which timer is attributed to the register pair of RCAP2H & RCAP2L for capture mode operation?
a. Timer 0
b. Timer 1
c. Timer 2
d. Timer 3
ANSWER:(c) Timer 2
26) Which registers are supposed to get copied into RCAP2H & RCAP2L respectively due to the transition at 8052 T2EX pin in the capture mode operation?
a. TH0 & TH1
b. TH1 & TH1
c. TH2 & TH2
d. All of the above
ANSWER: (c) TH2 & TH2
27) Which mode of timer 2 allow to hold the reload values with an assistance of RCAP2H & RCAP2L register pair?
a. 8 bit auto-reload mode
b. 16 bit auto reload mode
c. 8 bit capture mode
d. 16 bit capture mode
ANSWER: (b) 16 bit auto reload mode
28) Where should the pin 19 (XTAL1), acting as an input of inverting amplifier as well as part of an oscillator circuit, be connected under the application of external clock?
a. to XTAL2
b. to Vcc
c. to GND
d. to ALE
ANSWER: (c) to GND
29) Which port does not represent quasi-bidirectional nature of I/O ports in accordance to the pin configuration of 8051 microcontroller?
a. Port 0 (Pins 32-39)
b. Port 1 (Pins 1-8)
c. Port 2 (Pins 21-28)
d. Port 3 (Pins 10-17)
ANSWER: (a) Port 0 (Pins 32-39)
30) What is the required baud rate for an efficient operation of serial port devices in 8051 microcontroller?
a. 1200
b. 2400
c. 4800
d. 9600
ANSWER: (d) 9600
31) Which among the below mentioned functions does not belong to the category of alternate functions usually performed by Port 3 (Pins 10-17)?
a. External Interrupts
b. Internal Interrupts
c. Serial Ports
d. Read / Write Control signals
ANSWER: (b) Internal Interrupts
32) What is the constant activation rate of ALE that is optimized periodically in terms of an oscillator frequency?
a. 1 / 8
b. 1 / 6
c. 1 / 4
d. 1 / 2
ANSWER:(b) 1 / 6
33) Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution?
a. ALE
b. PSEN
c. EA
d. All of the above
ANSWER: (b) PSEN
34) Which memory allow the execution of instructions till the address limit of 0FFFH especially when the External Access (EA) pin is held high?
a. Internal Program Memory
b. External Program Memory
c. Both a & b
d. None of the above
ANSWER: (a) Internal Program Memory
35) Which value of disc capacitors is preferred or recommended especially when the quartz crystal is connected externally in an oscillator circuit of 8051?
a. 10 pF
b. 20 pF
c. 30 pF
d. 40 pF
ANSWER: (c) 30 pF
36) Why are the resonators not preferred for an oscillator circuit of 8051?
a. Because they do not avail for 12 MHz higher order frequencies
b. Because they are unstable as compared to quartz crystals
c. Because cost reduction due to its utility is almost negligible in comparison to total cost of microcontroller board
d. All of the above
ANSWER: (d) All of the above
37) Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in addition to the XTAL1 connectivity to ground level?
a. HMOS
b. CHMOS
c. CMOS
d. All of the abov
ANSWER: (a) HMOS
38) Which signal from CPU has an ability to respond the clocking value of D- flipflop (bit latch) from the internal bus?
a. Write-to-Read Signal
b. Write-to-Latch Signal
c. Read-to-Write Signal
d. Read-to-Latch Signal
ANSWER: (b) Write-to-Latch Signal
39) Which among the below mentioned statements are precisely related to quasi-bidirectional port?
a. Fixed high pull-up resistors are internally connected
b. Configuration in the form of input pulls the port at higher position whereas they get pulled lower when configured as a source current
c. It is possible to drive the pin as output at any duration when FET gets turned OFF for an input function
d. Upper pull-up FET is always OFF with the provision of ‘open-drain’ output pin for normal operation of port
a. A, B, C, D
b. A, B & C
c. A & B
d. C & D
ANSWER: (b) A, B & C
40) What happens when the pins of port 0 & port 2 are switched to internal ADDR and ADDR / DATA bus respectively while accessing an external memory?
a. Ports cannot be used as general-purpose Inputs/Outputs
b. Ports start sinking more current than sourcing
c. Ports cannot be further used as high impedance input
d. All of the above
ANSWER: (a) Ports cannot be used as general-purpose Inputs/Outputs
41) The upper 128 bytes of an internal data memory from 80H through FFH usually represent _______.
a. general-purpose registers
b. special function registers
c. stack pointers
d. program counters
ANSWER: (b) special function registers
42) What is the bit addressing range of addressable individual bits over the on-chip RAM?
a. 00H to FFH
b. 01H to 7FH
c. 00H to 7FH
d. 80H to FFH
ANSWER: (c) 00H to 7FH
43) What is the divisional range of program memory for internal and external memory portions respectively when enable access pin is held high (unity)?
a. 0000H – 0FFFH & 1000H – FFFFH
b. 0000H – 1000H & 0FFFH – FFFFH
c. 0001H – 0FFFH & 01FFH – FFFFH
d. None of the above
ANSWER: (a) 0000H – 0FFFH & 1000H – FFFFH
44) Consider the following statements. Which of them is/are correct in case of program execution related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status of EA pin is high (1)
b. External Program memory execution takes place from 0000H through 0FFFH only when the status of EA pin is low (0)
c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held low (0)
d. Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held high (1)
a. A & C
b. B & D
c. A & B
d. Only A
ANSWER: (b) B & D
45) How does the processor respond to an occurrence of the interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
ANSWER: (a) By Interrupt Service Subroutine
46) Which address/location in the program memory is supposed to get occupied when CPU jump and execute instantaneously during the occurrence of an interrupt?
a. Scalar
b. Vector
c. Register
d. All of the above
ANSWER: (b) Vector
47) Which location specify the storage/loading of vector address during the interrupt generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
ANSWER: (b) Program Counter
48) Match the following :
a. ISS —————————– 1. Monitors the status of interrupt pin
b. IER —————————– 2. Allows the termination of ISS
c. RETI ————————— 3. MCS-51 Interrupts Initialization
d. INTO ————————– 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
ANSWER:(c) A-1, B-3, C-2, D-4
49) What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt?
a. Edge-Triggering
b. Level Triggering
c. Both a & b
d. None of the above
ANSWER: (b) Level Triggering
50) Which among the below mentioned reasons is/are responsible for the generation of Serial Port Interrupt?
a. Overflow of timer/counter 1
b. High to low transition on pin INT1
c. High to low transition on pin INT0
d. Setting of either TI or RI flag
a. A & B
b. Only B
c. C & D
d. Only D
ANSWER: (d) Only D
51) What is the counting rate of a machine cycle in correlation to the oscillator frequency for timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
ANSWER: (b) 1 / 12
52) Which special function register play a vital role in the timer/counter mode selection process by allocating the bits in it?
a. TMOD
b. TCON
c. SCON
d. PCON
ANSWER:(a) TMOD
53) How many machine cycle/s is/are executed by the counters in 8051 in order to detect ‘1’ to ‘0’ transition at the external pin?
a. One
b. Two
c. Four
d. Eight
ANSWER: (b) Two
54) Which bit must be set in TCON register in order to start the ‘Timer 0’ while operating in ‘Mode 0’?
a. TR0
b. TF0
c. IT0
d. IE0
ANSWER: (a) TR0
55) Which among the following control/s the timer1 especially when it is configured as a timer in mode’0′, where gate and TR1 bits are attributed to be ‘1” in TMOD register?
a. TR1
b. External input at (INT1)
c. TF1
d. All of the above
ANSWER: (b) External input at (INT1)
56) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE enhancing the program counter to jump to another vector location?
a. Mode 0
b. Mode 1
c. Mode 2
d. Mode 3
ANSWER: (b) Mode 1
57) Consider the below generated program segment for initializing Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0
SJMP $
Which among the below mentioned program segments represent the correct code?
a. MOV SP, # 54 H
MOV TCON ,# 0010 0000 C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, # 54H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $
ANSWER: (c)
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
58) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an auto-reload mode (Mode 2) operation of the timer?
a. 125 μs
b. 250 μs
c. 256 μs
d. 1200 μs
ANSWER: (c) 256 μs
59) Which among the below mentioned sequence of program instructions represent the correct chronological order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B
2. MOV TL0, # 06H
3. MOV TH0, # 06H
4. SETB TR0
5. CPL p1.0
6. ORG 0000H
a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
ANSWER: (b) 6, 1, 3, 2, 4, 5
60) Why is it not necessary to specify the baud rate to be equal to the number of bits per second?
a. Because each bit is preceded by a start bit & followed by one stop bit
b. Because each byte is preceded by a start byte & followed by one stop byte
c. Because each byte is preceded by a start bit & followed by one stop bit
d. Because each bit is preceded by a start byte &followed by one stop byte
ANSWER: (c) Because each byte is preceded by a start bit & followed by one stop bit
61) Which factor/s is/are supposed to have the equal values at both phases of transmission and reception levels with an intimation of error-free serial communication?
a. Baud Rate
b. Number of data bits & stop bits
c. Status of Parity bits
d. All of the above
ANSWER: (d) All of the above
62) Which bits exhibit and signify the termination phase of the character transmission and reception in SCON special function register?
a. Control bits
b. Status bits
c. Both a & b
d. None of the above
ANSWER: (b) Status bits
63) Which two bits are supposed to be analyzed/tested for unity value (1) in SCON for the reception of byte in mode 1 serial communication?
a. RI & TI
b. REN & RB8
c. RI & REN
d. TI & RB8
ANSWER: (c) RI & REN
64) What is the bit transmitting or receiving capability of mode 1 in serial communication?
a. 8 bits
b. 10 bits
c. 11 bits
d. 12 bits
ANSWER: (b) 10 bits
65) Which pin in the shift register mode (Mode 0) of serial communication allow the data transmission as well as reception?
a. TXD
b. RXD
c. RB8
d. REN
ANSWER: (b) RXD
66) How is the baud rate determined on the basis of system clock frequency (fsc) in accordance to mode ‘0’ of serial communication?
a. (oscillator frequency) / 12
b. [2SMOD / 32] x (oscillator frequency) / [12 x (256 – (TH1)]
c. [2SMOD / 64] x (oscillator frequency)
d. 2SMOD/ 32 x (Timer 1 overflow rate)
ANSWER: (a) (oscillator frequency) / 12
67) Which serial modes possess the potential to support the multi-processor type of communication?
a. Modes 0 & 1
b. Modes 1 & 2
c. Modes 2 & 3
d. All of the above
ANSWER: (c) Modes 2 & 3
68) How does it become possible for 9th bit to differentiate the address byte from the data byte during the data transmission process in multiprocessor communication?
a. By recognizing 9th bit as ‘1’ for address byte & ‘0’ for data byte
b. By recognizing 9th bit as ‘0’ for address byte & ‘1’ for data byte
c. By recognizing 9th bit as ‘1’ for address as well as data bytes
d. By recognizing 9th bit as ‘0’ for address as well as data bytes
ANSWER: (a) By recognizing 9th bit as ‘1’ for address byte & ‘0’ for data byte
69) Which byte has the capability to interrupt the slave when SM2 bit is assigned to be ‘1’ after the initialization process in the multiprocessor mode of communication?
a. Address byte
b. Data byte
c. Both a & b
d. None of the above
ANSWER: (a) Address byte
70) Which bits of opcode specify the type of registers to be used in the register addressing mode?
a. LSB
b. MSB
c. Both a & b
d. None of the above
ANSWER: (a) LSB
71) Which base-register is preferred for address calculation of a byte that is to be accessed from program memory by base-register plus register-indirect addressing mode?
a. DPTR
b. PSW
c. PCON
d. All of the above
ANSWER: (a) DPTR
72) What does the symbol ‘#’ represent in the instruction MOV A, #55H?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype
ANSWER: (c) Immediate datatype
73) How many single byte, two-byte and three-byte instructions are supported by MCS-51 from the overall instruction set?
a. 55 – single byte, 35 two-byte & 21 three-byte instructions
b. 50 – single byte, 30 two-byte & 31 three-byte instructions
c. 42 – single byte, 45 two-byte & 24 three-byte instructions
d. 45 – single byte, 45 two-byte & 17 three-byte instructions
ANSWER: (d) 45 – single byte, 45 two-byte & 17 three-byte instructions
74) What kind of PSW flags remain unaffected by the data transfer instructions?
a. Auxillary Carry Flags
b. Overflow Flags
c. Parity Flags
d. All of the above
ANSWER: (d) All of the above
75) Which instruction should be adopted for moving an accumulator to the register from the below mentioned mnemonics?
a. MOV A, Rn
b. MOV A, @ Ri
c. MOV Rn, A
d. MOV direct, A
ANSWER:(c) MOV Rn, A
76) What does the instruction XCHD A, @Ri signify during the data transfer in the program execution?
a. Exchange of register with an accumulator
b. Exchange of direct byte with an accumulator
c. Exchange of indirect RAM with an accumulator
d. Exchange of low order digit indirect RAM with an accumulator
ANSWER: (d) Exchange of low order digit indirect RAM with an accumulator
77) Which flag allow to carry out the signed as well as unsigned addition and subtraction operations?
a. CY
b. OV
c. AC
d. F0
ANSWER: (b) OV
78) How many bytes are supposed to get occupied while subtracting indirect RAM from an accumulator along with borrow under the execution of SUBB A, @Ri?
a. 1
b. 2
c. 3
d. 4
ANSWER:(a) 1
79) What can be the oscillator period for the multiplication operation of A & B in accordance to 16-bit product especially in B:A registers?
a. 12
b. 24
c. 36
d. 48
ANSWER: (d) 48
80) Which form of instructions also belong to the category of logical instructions in addition to bitwise logical instructions?
a. Single-operand instructions
b. Rotate instructions
c. Swap instructions
d. All of the above
ANSWER: (d) All of the above
81) Which rotate instruction/s has an ability to modify CY flag by moving the bit-7 & bit-0 respectively to an accumulator?
a. RR & RL
b. RLC & RRC
c. RR & RRC
d. RL & RLC
ANSWER: (b) RLC & RRC
82) Which among the single operand instructions complement the accumulator without affecting any of the flags?
a. CLR
b. SETB
c. CPL
d. All of the above
ANSWER: (c) CPL
83) Match the following
a. JC rel ——————– 1. Jump if direct bit is set & clear bit
b. JNC rel —————— 2. Jump if direct bit is set
c. JB bit, rel ————— 3. Jump if direct bit is not set
d. JBC bit, rel ———— 4. Jump if carry is set
e. JNB bit, rel ————- 5. Jump if carry is not set
a. A-3, B-2, C-1, D-4, E-5
b. A-5, B-2, C-4, D-1, E-3
c. A-5, B-4, C-3, D-2, E-1
d. A-4, B-5, C-2, D-1, E-3
ANSWER: (d) A-4, B-5, C-2, D-1, E-3
84) What is the possible range of transfer control for 8-bit relative address especially in 2’s complement form with respect to the first byte of preceding instruction?
a. -115 to 132 bytes
b. -130 to 132 bytes
c. -128 to 127 bytes
d. -115 to 127 bytes
ANSWER:(c) -128 to 127 bytes
85) Which among the category of program branching instructions allow 16 bit address to be specified & can jump anywhere within 64K block of program memory?
a. Long jumps (LJMP)
b. Short jumps (SJMP)
c. Absolute jumps (AJMP)
d. All of the above
ANSWER: (a) Long jumps (LJMP)
86) Consider the below mentioned statements. Which among them is /are approved to be incorrect in case of calling instructions of program branching?
a. Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program memory block
b. Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory block
c. Short call instructions specify 16-bit address and subroutine within 4K program memory block
d. All long call and short call instructions specify 11 bit address and the calling subroutine within 16K program memory block
a. Only A
b. B & D
c. A & C
d. C & D
ANSWER: (d) C & D
87) Match the following instruction mnemonics with their description.
a. CJNE A,direct,rel ———— 1. Compare immediate to indirect and Jump if not equal
b. CJNE A,#data,rel ———— 2. Compare direct byte to accumulator and Jump if not equal
c. CJNE @Ri, #data,rel ——- 3. Compare immediate to register and Jump if not equal
d. CJNE Rn, # data rel ——– 4. Compare immediate to accumulator and Jump if not equal
a. A-1, B-2, C-3, D-4
b. A-2, B-4, C-1, D-3
c. A-4, B-3, C-2, D-1
d. A-2, B-4, C-3, D-1
ANSWER: (b) A-2, B-4, C-1, D-3
88) What is the correct chronological order of the following steps involved in the LCALL operation?
1. Load the value of 16-bit destination address to program counter
2. Increment of the program counter by value ‘3’
3. Storage of the higher byte of program counter on the stack
4. Increment of the stack pointer by value’1′
5. Storage of the lower byte of program counter on the stack
6. Increment in the value of stack pointer
a. 5, 3, 1, 6, 2, 4
b. 1, 3, 2, 5, 4, 6
c. 2, 4, 5, 6, 3, 1
d. 5, 3, 6, 2, 4, 1
ANSWER: (c) 2, 4, 5, 6, 3, 1
89) What is the status of stack pointer for the execution of PUSH and POP operations?
a. It gets post-decremented for PUSH & pre-incremented for POP
b. It gets pre-incremented for PUSH & post-decremented for POP
c. It gets pre-incremented for PUSH as well as POP
d. It gets post-decremented for PUSH as well as POP
ANSWER: (b) It gets pre-incremented for PUSH & post-decremented for POP
90) Which instructions contribute to an effective adoption or utilization of stack memory which usually plays a crucial role in storage of intermediate results?
a. ACALL
b. RETI
c. PUSH & POP
d. All of the above
ANSWER: (d) All of the above
91) Which functioning element of microcontroller generate and transmit the address of instructions to memory through internal bus?
a. Instruction Decoding Unit
b. Timing and Control Unit
c. Program Counter
d. Arithmetic Logic Unit
ANSWER: (c) Program Counter
92) How does the microcontroller communicate with the external peripherals/memory?
a. via I/O ports
b. via register arrays
c. via memory
d. All of the above
ANSWER: (a) via I/O ports
93) Why do the microprocessors possess very few bit manipulating instructions?
a. Because they mostly operate on bits/ word data
b. Because they mostly operate on byte/word data
c. Both a & b
d. None of the above
ANSWER: (b) Because they mostly operate on byte/word data
94) Which minimum mode signal is used for demultiplexing the data and address lines with the assistance of an external latch in a microprocessor while accessing memory segment?
a. INTA
b. DTE
c. HOLD
d. ALE
ANSWER: (d) ALE
95) Which word size is approved to be of greater importance for performing the small computational tasks along with its storage usability feature adopted by ASCII code?
a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit
ANSWER: (b) 8-bit
96) Which among the below stated statements does not exhibit the characteristic feature of 16-bit microcontroller?
a. Large program & data memory spaces
b. High speed
c. I/O Flexibility
d. Limited Control Applications
ANSWER: (d) Limited Control Applications
97) Which microcontrollers offer the provisional and salient software features of fault handling capability, interrupt vector efficiency and versatile addressing?
a. TMS 1000 (4 bit)
b. TMS 7500 (8 bit)
c. Intel 8096 (16 bit)
d. Intel 80960 (32 bit)
ANSWER: (d) Intel 80960 (32 bit)
98) Which category of microcontrollers acquire the complete hardware configuration on its chip so as to run the particular application?
a. Embedded Memory Microcontrollers
b. External Memory Microcontrollers
c. Both a & b
d. None of the above
ANSWER: (a) Embedded Memory Microcontrollers
99) External Memory Microcontrollers can overcome the limitations of insufficient in-built program and data memory by allowing the connections of external memory using _________
a. Serial Port Pins as address and data lines
b. Parallel Port Pins as address and data lines
c. Parallel Port Pins as address and control lines
d. Serial Port Pins as address and control lines
ANSWER: (b) Parallel Port Pins as address and data lines
100) How are the address and data buses removed in external memory type of microcontrollers?
a. Through demultiplexing by external latch & ALE signal
b. Through demultiplexing by external latch & DLE signal
c. Through multiplexing by external latch & DLE signal
d. Through multiplexing by external latch & ALE signal
ANSWER: (d) Through multiplexing by external latch & ALE signal
101) What are the significant designing issues/factors taken into consideration for RISC Processors?
a. Simplicity in Instruction Set
b. Pipeline Instruction Optimization
c. Register Usage Optimization
d. All of the above
ANSWER: (d) All of the above
102) What does the compact and uniform nature of instructions in RISC processors facilitate to?
a. Compiler optimization
b. Pipelining
c. Large memory footprints
d. None of the above
ANSWER: (b) Pipelining
103) Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?
a. Local Register
b. Temporary Register
c. Parameter Register
d. All of the above
ANSWER: (b) Temporary Register
104) Which architectural scheme has a provision of two sets for address & data buses between CPU and memory?
a. Harvard architecture
b. Von-Neumann architecture
c. Princeton architecture
d. All of the above
ANSWER: (a) Harvard architecture
105) Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture by most of the DSPs for streaming data?
a. Greater memory bandwidth
b. Predictable nature of bandwidth
c. Both a & b
d. None of the above
ANSWER: (c ) Both a & b
106) Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program and data fetching purposes?
a. Time Division Multiplexing
b. Frequency Division Multiplexing
c. Statistical Time Division Multiplexing
d. Code Division Multiplexing
ANSWER: (a) Time Division Multiplexing
107) Which feature deals with the fetching of next instruction during the execution of current instruction irrespective of the memory access?
a. Fetching
b. Pre-fetching
c. Fetch & Decoding
d. All of the above
ANSWER: (b) Pre-fetching
108) What are the essential tight constraint/s related to the design metrics of an embedded system?
a. Ability to fit on a single chip
b. Low power consumption
c. Fast data processing for real-time operations
d. All of the above
ANSWER: (d) All of the above
109) Which abstraction level undergo the compilation process by converting a sequential program into finite-state machine and register transfers while designing an embedded system?
a. System
b. Behaviour
c. RT
d. Logic
ANSWER: (b) Behaviour
110) Which characteristics of an embedded system exhibit the responsiveness to the assortments or variations in system’s environment by computing specific results for real-time applications without any kind of postponement?
a. Single-functioned Characteristics
b. Tightly-constraint Characteristics
c. Reactive & Real time Characteristics
d. All of the above
ANSWER: (c ) Reactive & Real time Characteristics
111) Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices of RS232?
a. CD & IR
b. DSR & DTR
c. RTS & CTS
d. None of the above
ANSWER: (c) RTS & CTS
112) Which among the below stated lines represent the handshaking variant usually and only controlled by the software in the handshaking process?
a. XON/ XOFF
b. DCD & GND
c. TxD & RxD
d. All of the above
ANSWER: (a )XON/ XOFF
113) Match the following registers with their functions :
a. Line Status Register ——————– 1. Set Up the communication parameters
b. Line Control Register —————— 2. Sharing of similar addresses
c. Transmit & Receive Buffers ——— 3. Status Determination of Tx & Rr
a. A-2, B-1, C-3
b. A-1, B-2, C-3
c. A-3, B-1, C-2
d. A-3, B-2, C-1
ANSWER: (c ) A-3, B-1, C-2
114) Which protocol standard of serial communication specify the bi-directional and half-duplex form of data transmission by allowing various numbers of drivers and receivers in bus configuration?
a. RS232
b. RS2485
c. RS422
d. RS423
ANSWER: ( b ) RS2485
115) What is the maximum device handling capacity of serial standard protocol RS485 in terms of drivers and receivers on a single line?
a. 8
b. 10
c. 16
d. 32
ANSWER: (d) 32
116) Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware handshake line during each time of the data transmission?
a. RTS Control
b. Send Data Control
c. Tri-State Control
d. Bit-wise Enable Timing Control
ANSWER: (b )Send Data Control
117) What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance to the I2c protocol specifications?
a. Bus Master
b. Bus Slaves
c. Bus Drivers
d. Bus Data Carriers
ANSWER: (a) Bus Master
118) What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carrying the information between the devices?
a. Uni-directional
b. Bi-directional
c. Multi-directional
d. None of the above
ANSWER: (b) Bi-directional
119) Which potential mode of operation indicate the frequent sending of byte to the slave corresponding to the reception of an acknowledge signal when it becomes desirable for the master to write to the slave during data transmission in I2C bus?
a. Master in master-transmit mode & Slave in slave-receive mode
b. Slave in slave-transmit mode & Master in master-receive mode
c. Master in master-transmit mode as well as master-receive mode
d. Slave in slave-transmit mode as well as slave-receive mode
ANSWER: (a) Master in master-transmit mode & Slave in slave-receive mode
120) Which processor has the necessity of manual optimization for the generation of assembly language code especially for the embedded systems?
a. RISC
b. CISC
c. Both a & b
d. None of the above
ANSWER: (b) CISC
121) Which among the below stated salient feature/s of SPI contribute to the wide range of its applicability?
a. Simple hardware interfacing
b. Full duplex communication
c. Low power requirement
d. All of the above
ANSWER: (d) All of the above
122) Which characteristic/s of two-wire interface (TWI) make it equally valuable in comparison to serial-peripheral interface (SPI)?
a. Less number of pins on IC packages than SPI
b. It possesses formal standard unlike SPI
c. Slave Addressing before communication & better hardware control
d. All of the above
ANSWER: (d) All of the above
123) What is the maximum speed of operating frequency exhibited by SPI as compared to that of TWI?
a. Less than 10 MHz
b. Greater than 10 MHz
c. Equal to 10 MHz
d. None of the above
ANSWER: (b) Greater than 10 MHz
124) Which development tool/program has the potential to allocate the specific addresses so as to load the object code into memory?
a. Loader
b. Locator
c. Library
d. Linker
ANSWER: (b) Locator
125) The assembler list file generated by an assembler mainly includes ________
a. binary codes
b. assembly language statements
c. offset for each instruction
d. All of the above
ANSWER: (d) All of the above
126) Which kind of assembler do not generate the programs in similar language as that used by micro-controllers by developing the program in high-level languages making them as machine independent?
a. Macro Assembler
b. Cross Assembler
c. Meta Assembler
d. All of the above
ANSWER: (b) Cross Assembler
127) What kind of address/es is /are usually assigned to program by the linker adopted in an execution of assembler?
a. Absolute Address
b. Relative Address starting from unity
c. Relative Addresss starting from zero
d. None of the above
ANSWER: (c) Relative Addresss starting from zero
128) What are the major form of functionalities associated to high-level language compilers?
a. Generation of an application program
b. Conversion of generated code from higher level language to machine-level language
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
129) Which development tool can facilitate the creation and modification of source programs in addition to assembly and higher -level languages?
a. Editor
b. Assembler
c. Debugger
d. High-level language Compiler
ANSWER: (a) Editor
130) EPROM Programming versions are of greater significance to designers for________
a. Debugging of hardware prototype
b. Debugging of software prototype
c. Loading the programs in microcontrollers
d. All of the above
ANSWER: (d) All of the above
131) It is a characteristic provision of some debuggers to stop the execution after each instruction because__________
a. it facilitates to analyze or vary the contents of memory and register
b. it facilitates to move the break point to a later point
c. it facilitates to rerun the program
d. it facilitates to load the object code program to system memory
ANSWER:(a) it facilitates to analyze or vary the contents of memory and register
132) Which component is replaced by an in-circuit emulator on the development board for testing purposes?
a. RAM
b. I/O Ports
c. Micro-controller IC
d. All of the above
ANSWER: (c) Micro-controller IC
133) It is feasible for an in-circuit emulator to terminate at the middle of the program execution so as to examine the contents of _________
a. memory
b. registers
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
134) Which operations are not feasible to perform by simulator programs in accordance to real time programming?
a. Memory Operations
b. I/O Operations
c. Register Operations
d. Debugging Operations
ANSWER: (b) I/O Operations
135) What is/are the possible way/s of displaying the data by logic analyzer?
a. Logic state format
b. Hexadecimal & Map format
c. Timing diagram format
d. All of the above
ANSWER: (d) All of the above
136) Which type of triggering allow the trigger qualifier circuit to compare the input data word with the word programmed by the user in logic analyzer?
a. Triggering from external input
b. Programmable Triggering
c. Both a & b
d. None of the above
ANSWER: (b) Programmable Triggering
137) Which mandatory contents can be visualized by the hexadecimal display format of a logic analyzer?
a. Data Bus
b. Address Bus
c. Both a & b
d. None of the above
ANSWER:(c) Both a & b
138) How many samples can be displayed before and after the trigger respectively if the trigger-pulse is delayed by center-trigger mode to display 1024 bit counts?
a. 512 & 512 samples respectively
b. 512 & 1024 samples respectively
c. 1024 & 512 samples respectively
d. 1024 & 1024 samples respectively
ANSWER: (d) 1024 & 1024 samples respectively
139) What is/are the consequences of driving the LED in the form of an output function?
a. Pin sources the current when made low without glowing LED
b. Pin sinks the current when made high without glowing LED
c. Pin sources the current when made high by glowing LED
d. Pin sinks the current when made low by glowing LED
ANSWER: (d) Pin sinks the current when made low by glowing LED
140) What is the possible range of current limiting resistor essential for lightening the LED in certain applications after pressing the push-button?
a. 25-55 Ω
b. 55-110 Ω
c. 110-220 Ω
d. 220-330 Ω
ANSWER: (d) 220-330 Ω
141) Which among the below given assertions exhibits the dependency of LED status over them, especially for LED and push button connection?
a. Closure of pushbutton
b. Low Output pin driven by microcontroller
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
142) What does the availability of LCD in 16 x 2 typical value indicate?
a. 16 lines per character with 2 such lines
b. 16 characters per line with 2 such lines
c. 16 pixels per line with 2 such sets
d. 16 lines per pixel with two such sets
ANSWER: (b) 16 characters per line with 2 such lines
143) Which control line/s act/s as an initiator by apprising LCD about the inception of data transmission by the microcontroller?
a. Enable (EN)
b. Register Select (RS)
c. Read/Write (RW)
d. All of the above
ANSWER: (a) Enable (EN)
144) The display operations in LCD are undertaken on EN line with ______
a. 0 to 1 transitions
b. 1 to 0 transitions
c. Both a & b
d. None of the above
ANSWER: (b) 1 to 0 transitions
145) When can a LCD display the text form of data?
a. only when RS line is high
b. only when RW line is high
c. only when RS line is low
d. only when RW line is low
ANSWER:(a) only when RS line is high
146) How does the instruction execute for read command ‘Get LCD Status’ in LCD?
a. By allowing EN line to go from low to high
b. By allowing EN line to go from high to low
c. By maintaining EN line to be stable
d. None of the above
ANSWER: (b) By allowing EN line to go from high to low
147) Match the HEX codes of LCD with their associated functions
a. 10H —————– 1) Shifting of cursor position to right
b. 14H —————– 2) Shifting of cursor position to left
c. 18H —————– 3) 2 lines & 5 x 7 character font
d. 38H —————– 4) Shifting of an entire display to the left
a. A-4, B–1, C-2, D-3
b. A-3, B–2, C-1, D-4
c. A-2, B-1, C-4, D-3
d. A-1, B–2, C-3, D-4
ANSWER: (c) A-2, B-1, C-4, D-3
148) How much delay is necessarily provided after the power-on-reset condition in order to overcome the predicaments related to valid power supply levels assigned to microcontroller and LCD?
a. 10 ms
b. 12 ms
c. 15 ms
d. 25 ms
ANSWER: (c) 15 ms
149) On which factors do the delay between two characters depend for display purposes in LCD?
a. Clock frequency
b. Display module
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
150) How many data lines are essential in addition to RS, EN and RW control lines for interfacing LCD with Atmel 89C51 microcontroller?
a. 3
b. 5
c. 8
d. 10
ANSWER:(c) 8
151) Which is the an alternative mechanism of preventing the software to be dependent on several delay factors along with an optimum time proficiency of checking LCD status at the interfacing level?
a. Polling of DB7 bit of the data bus
b. Updating the faster display in less time
c. Generalization of clock frequency and display module
d. All of the above
ANSWER: (a) Polling of DB7 bit of the data bus
152) What is the purpose of using Schmitt Trigger in the hardware circuit for key debouncing?
a. Noise Elimination
b. Improvement in Noise Immunity
c. Increase in Noise Figure
d. Reduction in Noise Temperature
ANSWER: (b) Improvement in Noise Immunity
153) Which lines are driven low under the software control during interfacing HEX keyboard with PIC 16F877?
a. Scan Lines
b. Return Lines
c. Both a & b
d. None of the above
ANSWER: (a) Scan Lines
154) Which keys are encoded for scan lines with ‘1101’ value (RB1 low) condition?
a. 0, 4, 8, C
b. 1, 5, 9, D
c. 2, 6, A, E
d. 3, 7, B, F
ANSWER: (c) 2, 6, A, E
155) What value of ‘B’ should be loaded in the TRISB register if return lines (RB7:RB4) and RB3:RB0 are supposed to be inputs and outputs respectively after the PORT B initialization?
a. 11000100
b. 11110011
c. 11110001
d. 11110000
ANSWER:(d) 11110000
156) Which essential operation should be performed while reading the external program byte on the data bus?
a. Latching of lower address byte
b. Latching of higher address byte
c. Latching of any addressable byte irrespective of priority level
d. None of the above
ANSWER: (a) Latching of lower address byte
157) Which bus/es acquire/s the potential of liberally receiving the code byte after addressing the lower order address byte?
a. Data bus
b. Address bus
c. Both a & b
d. None of the above
ANSWER: (a) Data bus
158) What happens when the RD signal becomes low during the read cycle?
a. Data byte gets loaded from external data memory to data bus
b. Address byte gets loaded from external data memory to address bus
c. Data byte gets loaded from external program memory to data bus
d. Address byte gets loaded from external program memory to address bus
ANSWER:(a) Data byte gets loaded from external data memory to data bus
159) Which among the below mentioned memory components possessess the potential of generating an ALE signal for the latching purpose of lower address byte in an external data memory?
a. CPU
b. Data Bus
c. Port 0
d. Port 1
ANSWER: (a) CPU
160) Which ports assist in addressing lower order and higher address bytes into the data bus simultaneously, while accessing the external data memory?
a. Port 0 & Port 1 respectively
b. Port 1 & Port 2 respectively
c. Port 0 & Port 2 respectively
d. Port 2 & Port 3 respectively
ANSWER: (c) Port 0 & Port 2 respectively
161) What happens when the latch is kept open once after the execution of the latch operation by allowing input digital data byte to appear at the output?
a. Variation in an input digital data
b. Output data remains constant despite changing input digital data
c. Variation in an output data with respect to input data variation
d. Cannot predict
ANSWER: (b) Output data remains constant despite changing input digital data
162) How is the latch interfacing with the microcontroller related to the number of digital output functions?
a. It increases the number of digital output functions in a time multiplexed manner
b. It decreases the number of digital output functions in a time multiplexed manner
c. It increases the number of digital output functions in a frequency multiplexed manner
d. It decreases the number of digital output functions in a frequency multiplexed manner
ANSWER: (a) It increases the number of digital output functions in a time multiplexed manner
163) What is the correct chronological order/sequence of steps associated with the latch operations given below?
a. Loading the data on output port
b. Increment in the digital output functions by using microcontroller pins
c. Application of latch enable signal to desired latch
a. A, B, C
b. A, C, B
c. C, A, B
d. B, A, C
ANSWER: (b) A, C, B
164) In an electromechanical relay, the necessity of connecting an external base resistance arises only _________
a. in the presence of an internal pull-up resistor
b. in the absence of an internal pull-up resistor
c. in the absence of an internal push-up resistor
d. in the presence of an internal push-up resistor
ANSWER: (b) in the absence of an internal pull-up resistor
165) Which diodes are employed in the electromechanical relays since the inductor current cannot be reduced to zero?
a. Tunnel Diode
b. Shockley Diode
c. Freewheeling Diode
d. Zener Diode
ANSWER: (c) Freewheeling Diode
166) Where do the power gets dissipated during the gradual decay of an inductor current (upto zero value) by turning OFF the transistor in an electromechanical relay?
a. Internal resistance of the coil
b. Internal Diode resistance
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
167) Which factors indicate the necessity of sample and hold circuit in the process of analog-to-digital conversion?
a. Instantaneous variation in an input signal
b. Analog-to-digital conversion time
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
168) Which pin/signal of ADC AD571 interfacing apprises about the accomplishment of data reading in the microcontroller so as to indicate ADC to get ready for the next data sample?
a. BLANK /CONVERT (high)
b. BLANK/DR (low)
c. DATA READY (DR)
d. All of the above
ANSWER:(a) BLANK /CONVERT (high)
169) Which errors are more likely to get generated by conversion time and ADC resolution respectively in accordance to the digital signal processing?
a. Sampling & Quantization Errors
b. Systematic & Random Errors
c. Overload & Underload Errors
d. None of the above
ANSWER: (a) Sampling & Quantization Errors
170) What is the purpose of blanking (BI) associated with the 7-segment display operations?
a. To turn ON the display
b. To turn OFF the display
c. To pulse modulate the brightness of display
d. To pulse modulate the lightness of display
a. B & C
b. A & D
c. A & B
d. C & D
ANSWER: (a) B & C
171) How are the port pins of microcontroller calculated for time-multiplexing types of display?
a. 4 + number of digits to be displayed
b. 4 raised to the number of digits to be displayed
c. 4 – number of digits to be displayed
d. 4 x number of digits to be displayed
ANSWER: (a) 4 + number of digits to be displayed
172) What does the RAM location at 44H indicates about the seven segment code?
a. 7-segment code for the third character
b. 7-segment code for the fourth character
c. Display of select code for third display
d. Display of select code for fourth display
ANSWER: (a) 7-segment code for the third character
173) How many clock pulses are confined by each machine cycle of Peripheral-Interface Controllers?
a. 4
b. 8
c. 12
d. 16
ANSWER: (a) 4
174) Which flags are more likely to get affected in status registers by Arithmetic and Logical Unit (ALU) of PIC 16 CXX on the basis of instructions execution?
a. Carry (C) Flags
b. Zero (Z) Flags
c. Digit Carry (DC) Flags
d. All of the above
ANSWER: (d) All of the above
175) What is the execution speed of instructions in PIC especially while operating at the maximum value of clock rate?
a. 0.1 μs
b. 0.2 μs
c. 0.4 μs
d. 0.8 μs
ANSWER: (b) 0.2 μs
176) Which operational feature of PIC allows it to reset especially when the power supply drops the voltage below 4V?
a. Built-in Power-on-reset
b. Brown-out reset
c. Both a & b
d. None of the above
ANSWER: (b)Brown-out reset
177) Which among the below stated reasons is/are responsible for the selection of PIC implementation/design on the basis of Harvard architecture instead of Von-Newman architecture?
a. Improvement in bandwidth
b. Instruction fetching becomes possible over a single instruction cycle
c. Independent bus access provision to data memory even while accessing the program memory
d. All of the above
ANSWER: (d) All of the above
178) Which among the below specified major functionalities is/are associated with the programmable timers of PIC?
a. Excogitation of Inputs
b. Handling of Outputs
c. Interpretation of internal timing for program execution
d. Provision of OTP for large and small production runs
a. Only C
b. C & D
c. A, B & D
d. A, B & C
ANSWER: (d) A, B & C
179) Which timer/s possess an ability to prevent an endless loop hanging condition of PIC along with its own on-chip RC oscillator by contributing to its reliable operation?
a. Power-Up Timer (PWRT)
b. Oscillator Start-Up Timer (OST)
c. Watchdog Timer (WDT)
d. All of the above
ANSWER: (c) Watchdog Timer (WDT)
180) Which among the CPU registers of PIC 16C6X/7X is not 8-bit wide?
a. Status Register
b. Program Counter Latch (PCLATH) Register
c. Program Counter Low Byte (PCL) Register
d. File Selection Register (FSR)
ANSWER: (b) Program Counter Latch (PCLATH) Register
181) Which register/s is/are mandatory to get loaded at the beginning before loading or transferring the contents to corresponding destination registers?
a. W
b. INDF
c. PCL
d. All of the above
ANSWER: (a) W
182) How many RPO status bits are required for the selection of two register banks?
a. 1
b. 2
c. 8
d. 16
ANSWER: (a) 1
183) The RPO status register bit has the potential to determine the effective address of______
a. Direct Addressing Mode
b. Indirect Addressing Mode
c. Immediate Addressing Mode
d. Indc. Watchdog Timer (WDT) exed Addressing Mode
ANSWER: (a) Direct Addressing Mode
184) Which status bits exhibit carry from lower 4 bits during 8-bit addition and are especially beneficial for BCD addition?
a. Carry bit (C)
b. Digits Carry bit (DC)
c. Both a & b
d. None of the above
ANSWER: (b) Digits Carry bit (DC)
185) Which statement is precise in relation to FSR, INDF and indirect addressing mode?
a. Address byte must be written in FSR before executing INDF instruction in indirect addressing mode
b. Address byte must be written in FSR after executing INDF instruction in indirect addressing mode
c. Address byte must be written in FSR at the same time during the execution of INDF instruction in indirect addressing mode
d. Address byte must be always written in FSR as it is independent of any instruction in indirect addressing mode
a. Only A
b. Only B
c. Only A & B
d. A & D
ANSWER: (a) Only A
186) Which among the below stated registers specify the address reachability within 7 bits of address independent of RP0 status bit register?
a. PCL
b. FSR
c. INTCON
d. All of the above
ANSWER: (d) All of the above
187) Where do the contents of PCLATH get transferred in the higher location of program counter while writing in PCL (Program Counter Latch)?
a. 11th bit
b. 12th bit
c. 13th bit
d. 14th bit
ANSWER: (c) 13th bit
188) Which condition/s of MCLR (master clear) pin allow to reset the PIC?
a. High
b. Low
c. Moderate
d. All of the above
ANSWER:(b) Low
189) Generation of Power-on-reset pulse can occur only after __________
a. the detection of increment in VDD from 1.5 V to 2.1 V
b. the detection of decrement in VDD from 2.1 V to 1.5 V
c. the detection of variable time delay on power up mode
d. the detection of current limiting factor
ANSWER: (a) the detection of increment in VDD from 1.5 V to 2.1 V
190) What is the rate of power up delay provided by an oscillator start-up timer while operating at XT, LP and HS oscillator modes?
a. 512 cycles
b. 1024 cycles
c. 2048 cycles
d. 4096 cycles
ANSWER: (b) 1024 cycles
191) Which kind of mode is favourable for MCLR pin for indulging in reset operations?
a. Normal mode
b. Sleep mode
c. Power-down mode
d. Any flexible mode
ANSWER: (b) Sleep mode
192) What is the purpose of using the start-up timers in an oscillator circuit of PIC?
a. For ensuring the inception and stabilization of an oscillator in a proper manner
b. For detecting the rise in VDD
c. For enabling or disabling the power-up timers
d. For generating the fixed delay of 72ms on power-up timers
ANSWER: (a) For ensuring the inception and stabilization of an oscillator in a proper manner
193) Which program location is allocated to the program counter by the reset function in Power-on-Reset (POR) action modes?
a. Initial address
b. Middle address
c. Final address
d. At any address reliable for reset operations
ANSWER: (a) Initial address
194) When does it become very essential to use the external RC components for the reset circuits?
a. Only if initialization is necessary for RAM locations
b. Only if VDD power-up slope is insufficient at a requisite level
c. Only if voltage drop exceeds beyond the limit
d. Only if current limiting factor increases rapidly
ANSWER: (b) Only if VDD power-up slope is insufficient at a requisite level
195) Which among the below mentioned PICs do not support the Brown-Out-Reset (BOR) feature?
a. PIC 16C66
B. PIC 16C74
C. PIC 16C61
D. PIC 16C71
a. A & B
b. C & D
c. A & C
d. B & D
ANSWER: (b) C & D
196) Which crucial feature/function of Brown-Out-Reset (BOR) makes the PIC to be completely unique and distinct from other microcontrollers?
a. It can reset the PIC automatically in running condition
b. It can reset the PIC even when the supply voltage increases above 4V
c. It can reset the PIC without enabling the power-up timer
d. All of the above
ANSWER: (a) It can reset the PIC automatically in running condition
197) What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in PIC?
a. CPU resets PIC once again in BOR mode
b. BOR reset mode gets disabled
c. PIC does not remain in BOR mode until the voltage increases irrespective of stability
d. Power-up timer kills 72ms more again
ANSWER: (a) CPU resets PIC once again in BOR mode
198) What output is generated by OSC2 pin in PIC oscillator comprising RC components for sychronizing the peripherals with PIC microcontroller?
a. (1/2) x frequency of OSC1
b. (1/4) x frequency of OSC1
c. (1/8) x frequency of OSC1
d. (1/16) x frequency of OSC1
ANSWER:(c) (1/8) x frequency of OSC1
199) Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources for operating at the range of 5- 200 kHz in PIC?
a. RC
b. LP (Low-Power Clocking)
c. XT
d. HS (High Speed)
ANSWER: (b) LP (Low-Power Clocking)
200) Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as compared to other clock sources?
a. High accuracy
b. Proficiency in time generation
c. Applicability in real-time operations
d. All of the above
ANSWER: (a) All of the above
201) What is the executable frequency range of High speed (HS) clocking method by using cystal/ ceramic/ resonator or any other external clock source?
a. 0-4 MHz
b. 5-200 KHz
c. 100kHz- 4 MHZ
d. 4-20 MHz
ANSWER: (d) 4-20 MHz
202) How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively?
a. 4 & 8 bits
b. 8 & 16 bits
c. 11 & 12 bits
d. 12 & 16 bits
ANSWER: (c) 11 & 12 bits
203) What location is attributed to ‘goto Mainline’ instruction in the program memory of PIC 16C61?
a. 000H
b. 004H
c. 001H
d. 011H
ANSWER: (a) 000H
204) When do the special address 004H get automatically loaded into the program counter?
a. After the execution of RESET action in program counter
b. After the execution of ‘goto Mainline ‘ instruction in the program memory
c. At the occurrence of interrupt into the program counter
d. At the clearance of program counter with no value
ANSWER: (c) At the occurrence of interrupt into the program counter
205) How many bits are utilized by the instruction of direct addressing mode in order to address the register files in PIC?
a. 2
b. 5
c. 7
d. 8
ANSWER:(c) 7
206) Which registers are adopted by CPU and peripheral modules so as to control and handle the operation of device inhibited in RFS?
a. General Purpose Register
b. Special Purpose Register
c. Special Function Registers
d. All of the above
ANSWER: (c) Special Function Registers
207) Which among the below specified registors are addressable only from bank1 of RFS?
a. PORTA (05H)
b. PORTB (06H)
c. FSR (04H)
d. ADCON0 (07H)
ANSWER: (a) PORTA (05H)
208) Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS?
a. INDF (80H)
b. TRISB (85H)
c. TRISA (85H)
d. PCLATH (8A)
ANSWER: (c) TRISA (85H)
209) Which bank of RFS has a provision of addressing the status register?
a. Only Bank 1
b. Only Bank 2
c. Either Bank 1 or Bank 2
d. Neither Bank 1 nor Bank 2
ANSWER: (c) Either Bank 1 or Bank 2
210) Which bit of OPTION register has a potential to decide the falling or rising edge sensitivity for the external interrupt INT?
a. RBPU
b. INTEDG
c. PSA
d. RTS
ANSWER: (b) INTEDG
211) Where are the prescalar assignments applied with a usage of PSA bit?
a. Only RTCC
b. Only Watchdog timer
c. Either RTCC or Watchdog timer
d. Neither RTCC nor Watchdog timer
ANSWER: (c) Either RTCC or Watchdog timer
212) Where is the exact specified location of an interrupt flag associated with analog-to-digital converter?
a. INTCON
b. ADCON0
c. ADRES
d. PCLATH
ANSWER: (b) ADCON0
213) Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register?
a. GIE
b. ADIE
c. RBIE
d. TOIE
ANSWER: (a) GIE
214) When does it become possible for a bit to get accessed from bank ‘0’ in the direct addressing mode of PICs?
a. Only when RPO bit is set ‘zero’
b. Only when RPO bit is set ‘1’
c. Only when RPO bit is utilized along with 7 lower bits of instruction code
d. Cannot Predict
ANSWER: (a) Only when RPO bit is set ‘zero’
215) When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of ‘interrupt on change’?
a. By configuring all the pins (RB4-RB7) as inputs
b. By configuring all the pins (RB4-RB7) as outputs
c. By configuring any one of the pins as inputs
d. By configuring any one of the pins as outputs
ANSWER: (a) By configuring all the pins (RB4-RB7) as inputs
216) Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output?
a. OR
b. AND
c. EX-OR
d. NAND
ANSWER: (a) OR
217) What is the purpose of acquiring two different bits from INTCON register for performing any interrupt operation in PIC 16C61 / 71?
a. One for enabling & one for disabling the interrupt
b. One for enabling the interrupt & one for its occurrence detection
c. One for setting or clearing the RBIE bit
d. None of the above
ANSWER: (b) One for enabling the interrupt & one for its occurrence detection
218) Which among the below specified combination of interrupts belong to the category of the PIC 16C61 / 71?
a. External, Timer/Counter & serial Port Interrupts
b. Internal, External & Timer/Counter Interrupts
c. External, Timer 0 & Port B Interrupts
d. Internal, External, Timer 0 & PortA Interrupts
ANSWER: (c) External, Timer 0 & Port B Interrupts
219) Which condition results in setting the GIE bit of INTCON automatically?
a. Execution of retfie instruction at the beginning of ISR
b. Execution of retfie instruction at the end of ISR
c. Execution of retfie instruction along with interrupt enable bit
d. Execution of retfie instruction along with interrupt disable bit
ANSWER: (b) Execution of retfie instruction at the end of ISR
220) What kind of external edge-sensitive interrupt is generated due to transition effect at pin RBO/INT?
a. INT
b. RBO
c. INTF
d. All of the above
ANSWER:(a) INT
221) Which bit-register pair plays a significant role in configuring the rising or falling edge triggering levels in external interrupts of PIC 16C61/71?
a. INTF bit – INTCON register
b. INTEDG bit – OPTION register
c. INT bit -INTCON register
d. INTE bit – OPTION register
ANSWER: (b) INTEDG bit – OPTION register
222) Consider the following statements. Which of them is /are incorrect?
a. By enabling INTE bit of an external interrupt can wake up the processor before entering into sleep mode.
b. INTF bit is set in INTCON only when a valid interrupt signal arrives at INT pin.
c. During the occurrence of interrupt, GIE bit is set in order to prevent any further interrupts.
d. goto instruction written in program memory cannot direct the program control to ISR.
a. A & B
b. C & D
c. Only A
d. Only C
ANSWER: (b) C & D
223) What is the purpose of setting TOIE bit in INTCON along with GIE bit?
a. For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
b. For setting the TOIE flag in INTCON due to generation of Timer 0 overflow interrupt
c. For setting the RBIF flag in INTCON due to generation of PORTB change interrupt
d. None of the above
ANSWER: (a) For setting the TOIF flag in INTCON due to generation of Timer 0 overflow interrupt
224) Where do the conversion interrupt flag (ADIF) end after an accomplishment of analog-to-digital (ADC) conversion process?
a. INTCON
b. ADCON0
c. OPTION
d. None of the above
ANSWER: (b) ADCON0
225) How much time is required for conversion per channel if PIC 16C71 possesses four analog channels, each comprising of 8-bits?
a. 10 μs
b. 15 μs
c. 20 μs
d. 30 μs
ANSWER: (c) 20 μs
226) How much delay is required to synchronize the external clock at TOCKI in Timer ‘0’ of PIC 16C61?
a. 2-cycles
b. 4-cycles
c. 6-cycles
d. 8-cycles
ANSWER: (a) 2-cycles
227) Which command enables the PIC to enter into the power down mode during the operation of watchdog timer (WDT)?
a. SLEEP
b. RESET
c. STATUS
d. CLR
ANSWER: (a) SLEEP
228) Which channel would be selected if the values of channel bits CHS0 & CHS1 are ‘1’ & ‘0’ respectively in ADC Status Register?
a. AIN0
b. AIN1
c. AIN2
d. AIN3
ANSWER: (c) AIN2
229) Which bit is mandatory to get initiated or set for executing the process of analog to digital conversion in ADCON0?
a. ADIF
b. ADON
c. Go/!Done
d. ADSC1
ANSWER: (c) Go/!Done
230) What would be the value of ADC clock source, if both the ADC clock bits are selected to be ‘1’?
a. FOSC/2
b. FOSC/8
c. FOSC/32
d. FRC
ANSWER: (d) FRC
231) The functionalities associated with the pins RA0- RA3 in ADCON1 are manipulated by __________
a. PCFG1 & PCG0
b. VREF
c. ADON
d. All of the above
ANSWER: (a) PCFG1 & PCG0
232) Which among the below mentioned aspect issues are supported by capture/compare/PWM modules corresponding to time in PIC 16F877?
a. Control
b. Measurement
c. Generation of pulse signal
d. All of the above
ANSWER: (d) All of the above
233) Which mode allows to deliver the contents of 16-bit timer into a SFR on the basis of rising/falling edge detection?
a. Capture Mode
b. Compare Mode
c. PWM Mode
d. MSSP Mode
ANSWER: (a) Capture Mode
234) What among the below specified functions is related to PWM mode?
a. Generation of an interrupt
b. Generation of rectangular wave with programmable duty cycle with an user assigned frequency
c. Variations in the status of an output pin
d. Detection of an exact point at which the change occurs in an input edge
ANSWER: (b) Generation of rectangular wave with programmable duty cycle with an user assigned frequency
235) What happens when the program control enters the Interrupt Service Subroutine (ISS) due to enabling of CCP1IE bit in PIE1 especially during the initialization of CCP1 Module in capture mode?
a. CCP1F bit gets cleared in PIR1 by detecting new capture event
b. GIE bit gets enabled
c. Contents of CCPR1L & CCPR1H are automatically copied in TMR1L & TMR1H respectively
d. Interrupt flag bit CCP1IF gets enabled in PIR
ANSWER: (a) CCP1F bit gets cleared in PIR1 by detecting new capture event
236) Which register is suitable for the corresponding count, if the measurement of pulse width is less than 65,535 μs along with the frequency of 4 MHz?
a. 4-bit register
b. 8-bit register
c. 16-bit register
d. 32-bit register
ANSWER: (c) 16-bit register
237) The capture operation in counter mode is feasible when mode of CCP module is _________
a. synchronized
b. asynchronized
c. synchronized as well as asynchronized
d. irrespective of synchronization
ANSWER: (a) synchronized
238) What is the fundamental role exhibited by the CCP module in compare mode in addition to timer 1?
a. To vary the pin status in accordance to the precisely controlled time
b. To vary the duty cycle of the rectified output
c. To vary the oscillator frequencies in order to receive larger periods
d. To vary the status of synchronization levels
ANSWER: (a) To vary the pin status in accordance to the precisely controlled time
239) How does the pin RC2/CCP1 get configured while initializing the CCP module in the compare mode of operation?
a. As an input by writing it in TRISC register
b. As an output by writing it in TRISC register
c. As an input without the necessity of writing or specifying it in TRISC register
d. Compare mode does not support pin RC2/CCP1 configuration CCP initialization
ANSWER: (b) As an output by writing it in TRISC register
240) Which flags of status register are most likely to get affected by the single-cycle increment and decrement instructions?
a. P Flags
b. C Flags
c. OV Flags
d. Z Flags
ANSWER: (d) Z Flags
241) Where does the comparison level occur for 16-bit contents in the compare mode operation?
a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0
ANSWER: (a) Between CCPR1 register & TMR1
242) Why are the pulse width modulated outputs required in most of the applications?
a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above
ANSWER: (b) To control average value of output variables
243) What would be the resolution value if oscillator and PWM frequencies are 16MHz and 2 MHz respectively?
a. 2
b. 3
c. 4
d. 8
ANSWER: (b) 3
244) How do the variations in an average value get affected by PWM period?
a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value
ANSWER: (b) Shorter the PWM period, faster will be the variation in an average value
245) Which among the below stated components should be filtered for determining the cut-off frequency corresponding to the PW period of low-pass filter?
a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components
ANSWER: (a) Fundamental FPWM & higher harmonics
246) Which among the below stated conditions are selected by the SSPCON & SSPSTAT control bits?
a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above
ANSWER: (d) All of the above
247) Which bit of SSPCON must be necessarily set so as to enable the synchronization of serial port?
a. WCOL
b. SSPOV
c. CKP
d. SSPEN
ANSWER: (d) SSPEN
248) What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave mode by enabling SS pin control?
a. 0000
b. 0100
c. 0010
d. 0001
ANSWER: (b) 0100
249) Which bits assist in determining the I2C bit rate during the initialization process of MSSP module in I2C mode?
a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above
ANSWER: (a) SSPADD
250) Which command/s should be essentially written for I2C input threshold selection and slew rate control operations?
a. SSPSTAT
b. SSPIF
c. ACKSTAT
d. All of the above
ANSWER: (a) SSPSTAT
251) Where does the baud rate generation occur and begins to count the bits required to get transmitted, after an execution (set) of BF flag?
a. SCL line
b. SDA line
c. Both a & b
d. None of the above
ANSWER: (b) SDA line
252) How many upper bits of SSPSR are comparable to the address located in SSPADD especially after the shifting of 8 bits into SSPSR under the execution of START condition?
a. 7
b. 8
c. 16
d. 32
ANSWER: (a) 7
253) Where should the value of TX9 bit be loaded during the 9 bit transmission in an asynchronous mode?
a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above
ANSWER: (a) TXSTA
254) What is the purpose of a special function register SPBRG in USART?
a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above
ANSWER: (a) To control the operation associated with baud rate generation
255) Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the data bits during the initialization process of USART in asynchronous mode?
a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity
ANSWER: (a) For ensuring the transmission of byte
256) How is the baud rate specified for high-speed (BRGH = 1) operation in an asynchronous mode?
a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1)
ANSWER: (b) FOSC / 16 (X + 1)
257) What is the status of shift clock supply in an USART synchronous mode?
a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally
ANSWER: (a) Master-internally, Slave-externally
258) Which bit plays a salient role in defining the master or slave mode in TXSTA register especially in synchronous mode?
a. RSRC
b. CSRC
c. SPEN
d. SYNC
ANSWER: (b) CSRC
259) Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines)?
a. TXSTA
b. RCSTA
c. Both a & b
d. None of the above
ANSWER: (b) RCSTA
260) Which among the below assertions represent the salient features of PIC in C-18 compiler?
a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above
ANSWER: (d) All of the above
261) Which command-line option of compiler exhibits the banner comprising overall number of errors, messages, warnings and version number after an accomplishment of the compilation process?
a. help
b. verbose
c. overlay
d. char
ANSWER: (b) verbose
262) In which aspects do the output functions specified in stdio.h differ from ANSI specified versions?
a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above
ANSWER: (d) All of the above
263) What does the ‘program idata’ section of data memory contain in C-18 Compiler?
a. statically assigned/allocated initialized user variables
b. statically assigned /allocated uninitialized user variables
c. only executable instructions
d. variables as well as constants
ANSWER: (a) statically assigned/allocated initialized user variables
264) Which instruction is applicable to set any bit while performing bitwise operation settings?
a. bcf
b. bsf
c. Both a & b
d. None of the above
ANSWER: (b) bsf
265) Where is the result stored after an execution of increment and decrement operations over the special – purpose registers in PIC?
a. File Register
b. Working Register
c. Both a & b
d. None of the above
ANSWER:(c) Both a & b
