Multiple Choice Questions and Answers on Microcontrollers and Applications(Part-5)

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1)   Where does the comparison level occur for 16-bit contents in the compare mode operation?

DRex Electronics

a. Between CCPR1 register & TMR1
b. Between CCPR1 & CCPR2 registers
c. Between CCPR2 register & TMR1
d. Between CCPR2 register & TMR0

ANSWER: (a) Between CCPR1 register & TMR1

2)   Why are the pulse width modulated outputs required in most of the applications?

a. To control average value of an input variables
b. To control average value of output variables
c. Both a & b
d. None of the above

ANSWER: (b) To control average value of output variables

3)   What would be the resolution value if oscillator and PWM frequencies are 16MHz and 2 MHz respectively?

a. 2
b. 3
c. 4
d. 8

ANSWER: (b) 3

4)   How do the variations in an average value get affected by PWM period?

a. Longer the PWM period, faster will be the variation in an average value
b. Shorter the PWM period, faster will be the variation in an average value
c. Shorter the PWM period, slower will be the variation in an average value
d. Longer the PWM period, slower will be the variation in an average value

ANSWER: (b) Shorter the PWM period, faster will be the variation in an average value

5)   Which among the below stated components should be filtered for determining the cut-off frequency corresponding to the PW period of low-pass filter?

a. Fundamental FPWM & higher harmonics
b. Resonant FPWM & higher harmonics
c. Slowly Varying DC components
d. Slowly Varying AC components

ANSWER: (a) Fundamental FPWM & higher harmonics

6)   Which among the below stated conditions are selected by the SSPCON & SSPSTAT control bits?

a. Slave Select mode in slave mode
b. Data input sample phase
c. Clock Rate in master mode
d. All of the above

ANSWER: (d) All of the above

7)   Which bit of SSPCON must be necessarily set so as to enable the synchronization of serial port?

a. WCOL
b. SSPOV
c. CKP
d. SSPEN

ANSWER: (d) SSPEN

8)   What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave mode by enabling SS pin control?

a. 0000
b. 0100
c. 0010
d. 0001

ANSWER: (b) 0100

9)   Which bits assist in determining the I2C bit rate during the initialization process of MSSP module in I2C mode?

a. SSPADD
b. SSPBUF
c. Both a & b
d. None of the above

ANSWER: (a) SSPADD

10)   Which command/s should be essentially written for I2C input threshold selection and slew rate control operations?

a. SSPSTAT
b. SSPIF
c. ACKSTAT
d. All of the above

ANSWER: (a) SSPSTAT

11)   Where does the baud rate generation occur and begins to count the bits required to get transmitted, after an execution (set) of BF flag?

a. SCL line
b. SDA line
c. Both a & b
d. None of the above

ANSWER: (b) SDA line

12)   How many upper bits of SSPSR are comparable to the address located in SSPADD especially after the shifting of 8 bits into SSPSR under the execution of START condition?

a. 7
b. 8
c. 16
d. 32

ANSWER: (a)  7

13)   Where should the value of TX9 bit be loaded during the 9 bit transmission in an asynchronous mode?

a. TXSTA
b. RCSTA
c. SPBRG
d. All of the above

ANSWER: (a) TXSTA

14)   What is the purpose of a special function register SPBRG in USART?

a. To control the operation associated with baud rate generation
b. To control an oscillator frequency
c. To control or prevent the false bit transmission of 9th bit
d. All of the above

ANSWER: (a) To control the operation associated with baud rate generation

15)   Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the data bits during the initialization process of USART in asynchronous mode?

a. For ensuring the transmission of byte
b. For ensuring the reception of byte
c. For ensuring the on-chip baud rate generation
d. For ensuring the 9th bit as a parity

ANSWER: (a) For ensuring the transmission of byte

16)   How is the baud rate specified for high-speed (BRGH = 1) operation in an asynchronous mode?

a. FOSC / 8 (X + 1)
b. FOSC / 16 (X + 1)
c. FOSC / 32 (X + 1)
d. FOSC / 64 (X + 1)

ANSWER: (b) FOSC / 16 (X + 1)

17)   What is the status of shift clock supply in an USART synchronous mode?

a. Master-internally, Slave-externally
b. Master-externally, Slave-internally
c. Master & Slave (both) – internally
d. Master & Slave (both) – externally

ANSWER: (a) Master-internally, Slave-externally

18)   Which bit plays a salient role in defining the master or slave mode in TXSTA register especially in synchronous mode?

a. RSRC
b. CSRC
c. SPEN
d. SYNC

ANSWER: (b) CSRC

19)   Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines)?

a. TXSTA
b. RCSTA
c. Both a & b
d. None of the above

ANSWER: (b)  RCSTA

20)   Which among the below assertions represent the salient features of PIC in C-18 compiler?

a. Transparent read/ write access to an external memory
b. Provision of supporting an inline assembly during the necessity of an overall control
c. Integration with MPLAB IDE for source-level debugging
d. All of the above

ANSWER: (d) All of the above

21)   Which command-line option of compiler exhibits the banner comprising overall number of errors, messages, warnings and version number after an accomplishment of the compilation process?

a. help
b. verbose
c. overlay
d. char

ANSWER: (b) verbose

22)   In which aspects do the output functions specified in stdio.h differ from ANSI specified versions?

a. Provision of MPLAB specific extensions
b. Floating-point Format Support
c. Data in Program Memory
d. All of the above

ANSWER: (d) All of the above

23)   What does the ‘program idata’ section of data memory contain in C-18 Compiler?

a. statically assigned/allocated initialized user variables
b. statically assigned /allocated uninitialized user variables
c. only executable instructions
d. variables as well as constants

ANSWER: (a) statically assigned/allocated initialized user variables

24)   Which instruction is applicable to set any bit while performing bitwise operation settings?

a. bcf
b. bsf
c. Both a & b
d. None of the above

ANSWER: (b) bsf

25)   Where is the result stored after an execution of increment and decrement operations over the special – purpose registers in PIC?

a. File Register
b. Working Register
c. Both a & b
d. None of the above

ANSWER:(c)  Both a & b

26)   Which flags of status register are most likely to get affected by the single-cycle increment and decrement instructions?

a. P Flags
b. C Flags
c. OV Flags
d. Z Flags

ANSWER: (d)  Z Flags