Multiple Choice Questions and Answers on Programmable Logic Device

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Q1. A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP.

a) GAL
b) CPLD
c) PAL
d) SPLD

Answer: c

Q2. What is another name for digital circuitry called sequential logic?

a) logic macrocell
b) logic array
c) flip-flop memory circuitry
d) inverter

Answer: c

Q3. When did the first PLD appear?

a) More than 10 years ago
b) More than 20 years ago
c) More than 30 years ago
d) More than 40 years ago

Answer: c

Q4. SPLDs, CPLDs, and FPGAs are all which type of device?

a) PAL
b) PLD
c) EPROM
d) SRAM

Answer: b

Q5. Cascade chains are closely associated with ________.

a) CLBs
b) SOP functions
c) logic expansion
d) all of the above

Answer: d

Q6. A GAL is essentially a ________.

a) non-reprogrammable PAL
b) PAL that is programmed only by the manufacturer
c) very large PAL
d) reprogrammable PAL

Answer: d

Q7. What is an OTP device?

a) Optical transporting port
b) Octal transmitting pixel
c) Operational topical portable
d) One-time programmable

Answer: d

Q8. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB?

a) 0
b) 5
c) 10
d) 20

Answer: b

Q9. Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:

a) the polarity fuse is restored
b) sent to an inverter for output
c) sent immediately to an output pin
d) passed to the AND function for output

Answer: b

Q10. ________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates.

a) Simplified AND gates
b) Fuses
c) Buffers
d) Latches

Answer: c

Q11.The difference between a PLA and a PAL is:

a) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane.
b) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane.
c) The PAL has more possible product terms than the PLA.
d) PALs and PLAs are the same thing.

Answer: a

Q12.ALM is the acronym for ________

a) Array Logic Matrix
b) Arithmetic Logic Module
c) Asynchronous Local Modulator
d) Adaptive Logic Module

Answer: d

Q13. The GAL16V8 has:

a) 16 dedicated inputs.
b) 8 special function pins.
c) 8 pins that are used as inputs or outputs.
d) All of the above

Answer: c

Q14. PALs tend to execute ________ logic.

a) SAP
b) SOP
c) PLA
d) SPD

Answer: b

Q15. How many pins are in an EDF10K70 package?

a) 70
b) 140
c) 240
d) 532

Answer: c

Q16. Which is not a part of a GAL16V8’s OLMC?

a) TSMUX
b) OMUX
c) FMUX
d) PSMUX

Answer: d

Q17. What is PROM?

a) SPLD
b) QPLD
c) HPLD
d) PLD

Answer: d

Q18.A slice consists of ________

a) only two logic cells
b) between 2 and 8 logic cells
c) up to 16 logic cells
d) a single CLB

Answer: a

Q19. Product terms are the outputs of which type of gate within a PLD array?

a) OR
b) XOR
c) AND
d) flip-flop

Answer: c

Q20. How many macrocells are in a MAX700S LAB?

a) 8
b) 16
c) 32
d) 64

Answer: b

Q21. Which is not a type of PLD?

a) SPLD
b) HPLD
c) CPLD
d) FPGA

Answer: b

Q22. An SPLD listed as 16H8 would have ________.

a) active-HIGH outputs
b) active-LOW outputs
c) variable-level outputs
d) latches at the outputs

Answer: a

Q23. Which type of PLD could be used to program basic logic functions?

a) PLA
b) PAL
c) CPLD
d) all the above

Answer: d

Q24. The complex programmable logic device (CPLD) contains several PAL-type simple programmable logic devices (SPLDs) called:

a) macrocells
b) microcells
c) AND/OR arrays
d) fuse-link arrays

Answer: a

Q25. What is an EPM7128S?

a) An Altera MAX7000S CPLD
b) An Altera UP2
c) A DeVry eSOC
d) A BSR PL DT-2

Answer: a

Q26. An SPLD listed as 22V10 has ________.

a) 10 inputs, 10 outputs, and requires a 22 V power source
b) 11 inputs, 11 outputs, and requires a 10 V power source
c) 22 inputs and 10 outputs
d) 10 inputs and 22 outputs

Answer: c

Q27. The Altera MAX 7000 series ________.

a) uses an E2PROM process technology
b) can have between 2 and 16 LABS and I/O control blocks
c) is available with DC supply voltages between 2.5 V and 5 V
d) all of the above

Answer: d

Q28.A macrocell basically contains ________.

a) a programmable AND-OR gate array and some input buffers
b) an OR-gate array and some output logic
c) an AND-OR gate array and some output logic
d) licensed programming

Answer: b

Q29.The complex programmable logic device (CPLD) features a(n) ________ type of memory.

a) volatile
b) nonvolatile
c) EPROM
d) volitile EPROM

Answer: b

Q30. Which of the following is true?

a) Altera uses PAL architecture and Xilinx uses PLA architecture.
b) Altera uses PLA architecture and Xilinx uses PAL architecture.
c) Altera and Xilinx both use PAL architecture.
d) Altera and Xilinx both use PLA architecture.

Answer: a

Q31. What is the status of a tristate output buffer on a MAX7000S family device?

a) It is permanently enabled or disabled.
b) It is controlled by one of the two global output enable pins.
c) It is controlled by other inputs or functions generated by other macrocells.
d) All of the above

Answer: d

Q32.GAL is an acronym for ________.

a) Generic Array Logic
b) General Array Logic
c) Giant Array Logic
d) Generic Analysis Logic

Answer: a

Q33. What gives a GAL its flexibility?

a) Its speed
b)Its reprogrammable EPROM
c) Its large logic arrays
d) Its programmable OLMCs

Answer: d

Q34. What programmable technology is used in FPGA devices?

a) SRAM
b) FLASH
c) Antifuse
d) All of the above

Answer: d

Q35. What is the input/output pin configuration of the GAL22V10?

a) 10 output pins and 12 input pins
b) 2 special-purpose pins
c) 8 pins that are either inputs or outputs
d) All of the above

Answer: a

Q36. What does a dot mean when placed on a PLD circuit diagram?

a) A point that is programmable
b) A point that cannot change
c) An intersection of logic blocks
d) An input or output point

Answer: b

Q37. FPGA is the acronym for ________.

a) Flexible Programming [of] Generic Assemblies
b) Field Programmable Generic Array
c) Field Programmable Gate Array
d) Field Programmer’s Gate Assembly

Answer: c

Q38. How many combinations are handled in an LUT?

a) 4
b) 8
c) 16
d) 32

Answer: c

Q39. Which is a mode of operation of the GAL16V8?

a) Simple mode
b) Complex mode
c) Registered mode
d) All of the above

Answer: d

Q40. Which of the following testing procedures uses the JTAG IEEE standard?

a) Bed-of-nails
b) Flying probe
c) EXTEST
d) Boundary scan

Answer: d

Q41. The macrocells in a PAL/GAL are located ________.

a) after the programmable AND arrays
b) ahead of the programmable AND arrays
c) at the input terminals
d) at the output terminals

Answer: a

Q42. The content of a simple programmable logic device (PLD) consists of:

a) fuse-link arrays
b) thousands of basic logic gates
c) advanced sequential logic functions
d) thousands of basic logic gates and advanced sequential logic functions

Answer: d

Q43. Which is a major digital system category?

a) Standard logic devices
b) ASICs
c) Microprocessor/DSP devices
d) All of the above

Answer: d

Q44. Field-programmable gate arrays (FGPAs) use ________ memory technology, which is ________.

a) DRAM, nonvolatile
b) SRAM, nonvolatile
c) SRAM, volatile
d) RAM, volatile

Answer: c

Q45.A PAL16L8 has:

a) 10 inputs and 8 outputs.
b) 8 inputs and 8 outputs.
c) 16 inputs and 16 outputs.
d) 16 inputs and 8 outputs.

Answer: a

Q46. Now many times can a GAL be erased and reprogrammed?

a) 0
b) At least 100
c) At least 1000
d) Over 10,000

Answer: b

Q47. MPGA stands for:

a) mass produced gated array.
b) Morgan-Phillips gated array.
c) memory programmed ROM.
d) mask programmed ROM.

Answer: d

Q48. Which of the following increases the number of product terms by borrowing unused product from other macrocells?

a) Shared expander
b) Parallel expander
c) Series expander
d) Slice expander

Answer: b

Q49.What does the Altera FLEX10K PLD use in place of AND and OR arrays?

a) Nothing, it uses AND and OR arrays.
b) Look-up tables
c) SRAM-based memory
d) HPLD architecture

Answer: b

Q50. PIA is an acronym for ________.

a) Programmable Interface Array
b) Post Integrated Array
c) Programmable Input Array
d) Programmable Interconnect Array

Answer: d

Q51. Which one of the following is an embedded function of the Stratix II FPGA?

a) AND-OR logic
b) Programmable SOP
c) Digital signal processing
d) None of the above

Answer: c

Q52. In an OLMC, where does the FMUX signal go?

a) OMUX
b) D flip-flop
c) Matrix
d) PAL

Answer: c

Q53. Which of the following testing procedures has one or more external moving parts?

a) Bed-of-nails
b) Flying probe
c) EXTEST
d) Boundary scan

Answer: b

Q54. CLB is the acronym for ________.

a) Configurable Logic Block
b) Configurable Logic Buffer
c) Critical Logic Buffer
d) Constant Logic Buffer

Answer: a

Q55. What can the GAL22V10 do that the GAL16V8 cannot?

a) It has an extra-large array.
b)It is in-system programmable.
c) It has twice the special function pins.
d) All of the above

Answer: b

Q56. A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.

a) output logic macrocell
b) look-up table
c) parallel logic expander
d) logic element

Answer: b

Q57. By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.

a) PAL
b) PLA
c) CPLD
d) EEPROM

Answer: a

Q58. A look-up table is simply a truth table with all the possible output connections listed with their desired input response.

a) True
b) False

Answer: b

Q59.The final step in the device programming sequence is ________.

a) compiling
b) downloading
c) simulation
d) synthesis

Answer: b

Q60. Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs.

a) 4,16
b) 8,16
c) 4,12
d) 6,12

Answer: a