Why is there a bootstrap capacitor in all DCDC chip designs?

In the past electronic product design, we often choose to DCDC chips, often encountered in the selection process of DCDC chips have synchronous rectification and asynchronous rectification of two kinds(source: Easybom.)

We often see a bootstrap capacitor in such DCDC circuits, often marked on the chip pin BS or BST, as shown in the figure below, Tuoerl Micro’s TMI3494, which chose a 0.1uF capacitor used to bootstrap.

So, why is it called bootstrap here? We can analyze it step by step.

First of all, based on the Buck topology of the DCDC chip, the bootstrap capacitor is not necessary, such as the following Tuoer Micro’s TMI3493, his schematic does not have this bootstrap capacitor.

The main difference between TMI3493 and TMI3494 is two points:

TMI3494 is asynchronous rectification, TMI3493 is synchronous finishing, which can be seen from the schematic diode.

The internal high-side MOS of the TMI3494 is NMOS, while the high-side MOS of the TMI3493 is PMOS.

Yes, the presence or absence of bootstrap capacitance depends on the type of MOS tube used in the chip design.

The MOS tube on and off

To study the origins of this bootstrap, let’s first look at the MOS on and off.

From the above, we first need to look at the switching situation in the NMOS and PMOS power topologies.

The Bcuk circuit shown above uses PMOS as the switch for the chopper control, so we know that we only need to apply a negative voltage to the Vgs of Q1 to turn on the MOS tube Q1.

However, from the production process of the MOS tube, we know that the on-current of PMOS is often not very large, and at the same cost, the on-current of NMOS can be much larger, which means that the Rdson can be relatively low.

Therefore, in a Buck circuit, the switching tube is replaced from PMOS to NMOS, as shown in the figure below.

So the question is, how do we give a high level on MOS Q1 after replacing the PMOS with NMOS in the Bcuk circuit?

The maximum system voltage is 40V, so from the above diagram, we need more than 45V on the gate of the MOS in order to make Q1 fully conductive.

Therefore, in the design of DC-DC chips using NMOS on the high side MOS, a circuit is needed to bootstrap, that is, to generate a voltage higher than the system input voltage to turn on the high side NMOS, and because of the size of the capacitor, it is difficult to be integrated in the IC, so most of the DC-DC chips require the user to place the bootstrap capacitor on the outside.

Analysis of bootstrap capacitance in H-bridge driving circuit

I would like to use the H-bridge drive circuit in the MOS and MOSDriver circuit to analyze the bootstrap capacitance of the working principle and process, because the use of H-bridge circuits to promote inductive loads, and DCDC chips to promote the energy-storage inductors to reduce the voltage when the working principle is basically the same.

First of all, the two MOS tubes of the upper and lower bridges cannot conduct at the same time, so when the lower tube conducts, the red arrow in the above figure is labeled as the charging circuit of the bootstrap capacitor. At this stage, both ends of the bootstrap capacitor AB are charged to 12V.

In the next stage, the lower tube is turned off and the S-pole of the upper tube Q1 is floating. The IR2014 internally links the VB pin to the HO pin to connect a fully-charged bootstrap capacitor in parallel with the GS poles of Q1, so that Vgs = 12V, which causes Q1 to turn on.

This cycle, after the upper tube is turned off, the lower tube is turned on, and then continue to charge the bootstrap capacitor in preparation for the next time the upper tube is turned on.

Synchronous DCDC circuit in the bootstrap capacitor

Synchronous DC-DC chip in the bootstrap capacitor principle and the above mentioned H-bridge drive is very similar, we look at the internal block diagram of synchronous DC-DC chip to see the bootstrap circuit.

Block diagram, the two green circles of the VCC is the DC-DC chip internal voltage regulator out of a can drive the MOS open voltage, but also for other logic circuits within the chip, here you can understand for the previous section of the IR2014 input voltage 12V.

Then, just like the logic in the H-bridge circuit, when the low-side MOS tube is turned on by the LS Driver (here you can directly use VCC to drive it because it is a low-side NMOS), the bootstrap capacitor circuit is charged through the circuit with the red arrow, and it will be charged up to the voltage of VCC between the voltage of V+ and V- on both ends of the bootstrap capacitor.

At this point, the buck circuit is in the current-continuing state, so the green arrow indicates the current-continuing loop between the power output and the load circuit.

When the continuity is finished, the low-side NMOS will be turned off, and the high-side NMOS will be turned on by the HS Driver to replenish the inductor by connecting the C1 capacitor directly to the GS terminals of the high-side NMOS.

If the high-side NMOS in the DC-DC is replaced by a PMOS, there is no need to go through the trouble of charging a capacitor, and the high-side PMOS can be turned on by directly giving a voltage lower than the system input voltage VIN.

Asynchronous DCDC bootstrap capacitor

Below, we look through a picture, for asynchronous DCDC chip, its bootstrap capacitor charging circuit is how, because the asynchronous DCDC does not have a low-side MOS tube, it is designed to rely on the external design of a Schottky diode to renew the current, so the chip’s internal design is still different.

We can see that the asynchronous DC-DC chip in the lower side of the bridge designed a small MOS tube, and series a diode (blue circle), the reason why this is a small MOS tube, the reason is that it has a diode in series, in the process of renewing the current, the high-current circuit will only flow through the external Schottky diode, and will not affect the charging circuit of the bootstrap capacitor.

The red arrow points to the circuit is the bootstrap capacitor charging circuit, this time we understand it, in the asynchronous DC-DC chip, the engineer is preset a small MOS tube to control the bootstrap capacitor charging circuit.

Bootstrap capacitor selection

Understand the principle of bootstrap capacitors, in fact, for bootstrap capacitor selection can also be handy, the manual will generally mark it out, it is the theoretical rated voltage is the voltage of the DCDC chip VCC.

Manual will generally recommend, here generally choose 10V or 16V MLCC can be, after all, now the MOS tube Vth more and more also low, basically within 5V can be completely open.